From: Stefan Hajnoczi <stefanha@redhat.com>
To: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: peter.maydell@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net
Subject: Re: [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G)
Date: Fri, 19 Feb 2016 13:18:01 +0000 [thread overview]
Message-ID: <20160219131801.GA16902@stefanha-x1.localdomain> (raw)
In-Reply-To: <1455843725-88869-1-git-send-email-sagark@eecs.berkeley.edu>
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On Thu, Feb 18, 2016 at 05:02:04PM -0800, Sagar Karandikar wrote:
> - The devices in hw/riscv/htif are intended to mimic the experimental devices
> that we use with our RISC-V test chips. These will be removed and replaced
> with "real" devices once there is better software support in the OS/bootloader
> ports.
You can use QEMU's "machine types" concept to support different hardware
configurations. For the time being, htif could be the default. In the
future maybe another variant will take over that provides the default
hardware and firmware environment for production RISC-V machines.
If you look at QEMU ARM there are several different machine types for
various ARM boards.
Stefan
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next prev parent reply other threads:[~2016-02-19 13:18 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-19 1:02 [Qemu-devel] [RFC 0/1] riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G) Sagar Karandikar
2016-02-19 1:02 ` [Qemu-devel] [RFC 1/1] " Sagar Karandikar
2016-02-19 13:18 ` Stefan Hajnoczi [this message]
2016-02-19 13:22 ` [Qemu-devel] [RFC 0/1] " Peter Maydell
2016-02-19 17:18 ` Stefan Hajnoczi
2016-02-23 21:02 ` Richard Henderson
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