From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48093) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWnpL-0002hm-HH for qemu-devel@nongnu.org; Fri, 19 Feb 2016 11:22:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1aWnpH-0007G6-ED for qemu-devel@nongnu.org; Fri, 19 Feb 2016 11:22:43 -0500 Received: from mx1.redhat.com ([209.132.183.28]:49349) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1aWnpH-0007Fo-9D for qemu-devel@nongnu.org; Fri, 19 Feb 2016 11:22:39 -0500 Date: Fri, 19 Feb 2016 17:22:33 +0100 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Message-ID: <20160219162228.GA24445@potion.brq.redhat.com> References: <1455852618-5224-1-git-send-email-peterx@redhat.com> <56C6BA42.1050302@web.de> <20160219074300.GC17229@pxdev.xzpeter.org> <56C6D3A0.9070302@web.de> <20160219092931.GD17229@pxdev.xzpeter.org> <56C6E734.90204@redhat.com> <20160219113411.GA11961@pxdev.xzpeter.org> <56C6FFED.4050408@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <56C6FFED.4050408@web.de> Subject: Re: [Qemu-devel] [PATCH 00/13] IOMMU: Enable interrupt remapping for Intel IOMMU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: Peter Maydell , Rita Sinha , ehabkost@redhat.com, mst@redhat.com, jasowang@redhat.com, qemu-devel@nongnu.org, Peter Xu , imammedo@redhat.com, Paolo Bonzini , rth@twiddle.net 2016-02-19 12:43+0100, Jan Kiszka: > On 2016-02-19 12:34, Peter Xu wrote: >> On Fri, Feb 19, 2016 at 10:58:12AM +0100, Paolo Bonzini wrote: >>> >>> The source ID can be passed to the IOMMU using the MemTxAttrs mechanism. >> >> I see that MemTxAttrs is not enabled yet? It's dropped in all the >> accessors like memory_region_write_accessor()? > > That would be a pity. How much work remains to fix that? Putting Peter > Maydell on CC who apparently started this extension. memory_region_dispatch_write() uses write_with_attrs, so I think we only need to use one for MSI region and add attributes to direct writers (like HPET and IOAPIC, because normal PCI devices should be passing correct attributes). > ... >>> FWIW, Radim was thinking of interrupt remapping in the kvm-ioapic, which >>> we have decided to set aside. > >> Does it mean that we are planning not to support kernel_irqchip for >> IR? Any quick reason? > > The reason to split up the kernel irqchip is to reduce code complexity > and, thus, attack surface of the kernel-side interface towards the > guest. So, extending the "classic" in-kernel support with yet another > feature is not really supporting that goal. A fear of regressions after forcing people to switch from kernel ioapic to qemu ioapic is the only argument for in-kernel support. We'd like to use split irqchip even without IR.