From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47533) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ad615-0006kT-L2 for qemu-devel@nongnu.org; Mon, 07 Mar 2016 20:00:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ad612-0003Dz-NT for qemu-devel@nongnu.org; Mon, 07 Mar 2016 20:00:51 -0500 Date: Tue, 8 Mar 2016 11:37:02 +1100 From: David Gibson Message-ID: <20160308003702.GQ22546@voom.fritz.box> References: <1457317586-15122-1-git-send-email-david@gibson.dropbear.id.au> <1457317586-15122-2-git-send-email-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="oDto3OTLsk6uOlQH" Content-Disposition: inline In-Reply-To: <1457317586-15122-2-git-send-email-david@gibson.dropbear.id.au> Subject: Re: [Qemu-devel] [PATCHv2 1/3] target-ppc: Split out SREGS get/put functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: gkurz@linux.vnet.ibm.com, aik@ozlabs.ru Cc: lvivier@redhat.com, thuth@redhat.com, qemu-ppc@nongnu.org, agraf@suse.de, qemu-devel@nongnu.org --oDto3OTLsk6uOlQH Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Mar 07, 2016 at 01:26:24PM +1100, David Gibson wrote: > Currently the getting and setting of Power MMU registers (sregs) take up > large inline chunks of the kvm_arch_get_registers() and > kvm_arch_put_registers() functions. Especially since there are two > variants (for Book-E and Book-S CPUs), only one of which will be used in > practice, this is pretty hard to read. >=20 > This patch splits these out into helper functions for clarity. No > functional change is expected. >=20 > Signed-off-by: David Gibson Greg, or Alexey, can I can an R-b for this one as well? > --- > target-ppc/kvm.c | 421 ++++++++++++++++++++++++++++++-------------------= ------ > 1 file changed, 228 insertions(+), 193 deletions(-) >=20 > diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c > index d67c169..8a762e8 100644 > --- a/target-ppc/kvm.c > +++ b/target-ppc/kvm.c > @@ -867,6 +867,44 @@ static int kvm_put_vpa(CPUState *cs) > } > #endif /* TARGET_PPC64 */ > =20 > +static int kvmppc_put_books_sregs(PowerPCCPU *cpu) > +{ > + CPUPPCState *env =3D &cpu->env; > + struct kvm_sregs sregs; > + int i; > + > + sregs.pvr =3D env->spr[SPR_PVR]; > + > + sregs.u.s.sdr1 =3D env->spr[SPR_SDR1]; > + > + /* Sync SLB */ > +#ifdef TARGET_PPC64 > + for (i =3D 0; i < ARRAY_SIZE(env->slb); i++) { > + sregs.u.s.ppc64.slb[i].slbe =3D env->slb[i].esid; > + if (env->slb[i].esid & SLB_ESID_V) { > + sregs.u.s.ppc64.slb[i].slbe |=3D i; > + } > + sregs.u.s.ppc64.slb[i].slbv =3D env->slb[i].vsid; > + } > +#endif > + > + /* Sync SRs */ > + for (i =3D 0; i < 16; i++) { > + sregs.u.s.ppc32.sr[i] =3D env->sr[i]; > + } > + > + /* Sync BATs */ > + for (i =3D 0; i < 8; i++) { > + /* Beware. We have to swap upper and lower bits here */ > + sregs.u.s.ppc32.dbat[i] =3D ((uint64_t)env->DBAT[0][i] << 32) > + | env->DBAT[1][i]; > + sregs.u.s.ppc32.ibat[i] =3D ((uint64_t)env->IBAT[0][i] << 32) > + | env->IBAT[1][i]; > + } > + > + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_SREGS, &sregs); > +} > + > int kvm_arch_put_registers(CPUState *cs, int level) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > @@ -920,39 +958,8 @@ int kvm_arch_put_registers(CPUState *cs, int level) > } > =20 > if (cap_segstate && (level >=3D KVM_PUT_RESET_STATE)) { > - struct kvm_sregs sregs; > - > - sregs.pvr =3D env->spr[SPR_PVR]; > - > - sregs.u.s.sdr1 =3D env->spr[SPR_SDR1]; > - > - /* Sync SLB */ > -#ifdef TARGET_PPC64 > - for (i =3D 0; i < ARRAY_SIZE(env->slb); i++) { > - sregs.u.s.ppc64.slb[i].slbe =3D env->slb[i].esid; > - if (env->slb[i].esid & SLB_ESID_V) { > - sregs.u.s.ppc64.slb[i].slbe |=3D i; > - } > - sregs.u.s.ppc64.slb[i].slbv =3D env->slb[i].vsid; > - } > -#endif > - > - /* Sync SRs */ > - for (i =3D 0; i < 16; i++) { > - sregs.u.s.ppc32.sr[i] =3D env->sr[i]; > - } > - > - /* Sync BATs */ > - for (i =3D 0; i < 8; i++) { > - /* Beware. We have to swap upper and lower bits here */ > - sregs.u.s.ppc32.dbat[i] =3D ((uint64_t)env->DBAT[0][i] << 32) > - | env->DBAT[1][i]; > - sregs.u.s.ppc32.ibat[i] =3D ((uint64_t)env->IBAT[0][i] << 32) > - | env->IBAT[1][i]; > - } > - > - ret =3D kvm_vcpu_ioctl(cs, KVM_SET_SREGS, &sregs); > - if (ret) { > + ret =3D kvmppc_put_books_sregs(cpu); > + if (ret < 0) { > return ret; > } > } > @@ -1014,12 +1021,197 @@ static void kvm_sync_excp(CPUPPCState *env, int = vector, int ivor) > env->excp_vectors[vector] =3D env->spr[ivor] + env->spr[SPR_BOOKE_I= VPR]; > } > =20 > +static int kvmppc_get_booke_sregs(PowerPCCPU *cpu) > +{ > + CPUPPCState *env =3D &cpu->env; > + struct kvm_sregs sregs; > + int ret; > + > + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); > + if (ret < 0) { > + return ret; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_BASE) { > + env->spr[SPR_BOOKE_CSRR0] =3D sregs.u.e.csrr0; > + env->spr[SPR_BOOKE_CSRR1] =3D sregs.u.e.csrr1; > + env->spr[SPR_BOOKE_ESR] =3D sregs.u.e.esr; > + env->spr[SPR_BOOKE_DEAR] =3D sregs.u.e.dear; > + env->spr[SPR_BOOKE_MCSR] =3D sregs.u.e.mcsr; > + env->spr[SPR_BOOKE_TSR] =3D sregs.u.e.tsr; > + env->spr[SPR_BOOKE_TCR] =3D sregs.u.e.tcr; > + env->spr[SPR_DECR] =3D sregs.u.e.dec; > + env->spr[SPR_TBL] =3D sregs.u.e.tb & 0xffffffff; > + env->spr[SPR_TBU] =3D sregs.u.e.tb >> 32; > + env->spr[SPR_VRSAVE] =3D sregs.u.e.vrsave; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { > + env->spr[SPR_BOOKE_PIR] =3D sregs.u.e.pir; > + env->spr[SPR_BOOKE_MCSRR0] =3D sregs.u.e.mcsrr0; > + env->spr[SPR_BOOKE_MCSRR1] =3D sregs.u.e.mcsrr1; > + env->spr[SPR_BOOKE_DECAR] =3D sregs.u.e.decar; > + env->spr[SPR_BOOKE_IVPR] =3D sregs.u.e.ivpr; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_64) { > + env->spr[SPR_BOOKE_EPCR] =3D sregs.u.e.epcr; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { > + env->spr[SPR_BOOKE_SPRG8] =3D sregs.u.e.sprg8; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_IVOR) { > + env->spr[SPR_BOOKE_IVOR0] =3D sregs.u.e.ivor_low[0]; > + kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); > + env->spr[SPR_BOOKE_IVOR1] =3D sregs.u.e.ivor_low[1]; > + kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); > + env->spr[SPR_BOOKE_IVOR2] =3D sregs.u.e.ivor_low[2]; > + kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); > + env->spr[SPR_BOOKE_IVOR3] =3D sregs.u.e.ivor_low[3]; > + kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); > + env->spr[SPR_BOOKE_IVOR4] =3D sregs.u.e.ivor_low[4]; > + kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); > + env->spr[SPR_BOOKE_IVOR5] =3D sregs.u.e.ivor_low[5]; > + kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); > + env->spr[SPR_BOOKE_IVOR6] =3D sregs.u.e.ivor_low[6]; > + kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); > + env->spr[SPR_BOOKE_IVOR7] =3D sregs.u.e.ivor_low[7]; > + kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); > + env->spr[SPR_BOOKE_IVOR8] =3D sregs.u.e.ivor_low[8]; > + kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); > + env->spr[SPR_BOOKE_IVOR9] =3D sregs.u.e.ivor_low[9]; > + kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); > + env->spr[SPR_BOOKE_IVOR10] =3D sregs.u.e.ivor_low[10]; > + kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); > + env->spr[SPR_BOOKE_IVOR11] =3D sregs.u.e.ivor_low[11]; > + kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); > + env->spr[SPR_BOOKE_IVOR12] =3D sregs.u.e.ivor_low[12]; > + kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); > + env->spr[SPR_BOOKE_IVOR13] =3D sregs.u.e.ivor_low[13]; > + kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); > + env->spr[SPR_BOOKE_IVOR14] =3D sregs.u.e.ivor_low[14]; > + kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); > + env->spr[SPR_BOOKE_IVOR15] =3D sregs.u.e.ivor_low[15]; > + kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); > + > + if (sregs.u.e.features & KVM_SREGS_E_SPE) { > + env->spr[SPR_BOOKE_IVOR32] =3D sregs.u.e.ivor_high[0]; > + kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); > + env->spr[SPR_BOOKE_IVOR33] =3D sregs.u.e.ivor_high[1]; > + kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33); > + env->spr[SPR_BOOKE_IVOR34] =3D sregs.u.e.ivor_high[2]; > + kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34); > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_PM) { > + env->spr[SPR_BOOKE_IVOR35] =3D sregs.u.e.ivor_high[3]; > + kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR35); > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_PC) { > + env->spr[SPR_BOOKE_IVOR36] =3D sregs.u.e.ivor_high[4]; > + kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36); > + env->spr[SPR_BOOKE_IVOR37] =3D sregs.u.e.ivor_high[5]; > + kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37); > + } > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { > + env->spr[SPR_BOOKE_MAS0] =3D sregs.u.e.mas0; > + env->spr[SPR_BOOKE_MAS1] =3D sregs.u.e.mas1; > + env->spr[SPR_BOOKE_MAS2] =3D sregs.u.e.mas2; > + env->spr[SPR_BOOKE_MAS3] =3D sregs.u.e.mas7_3 & 0xffffffff; > + env->spr[SPR_BOOKE_MAS4] =3D sregs.u.e.mas4; > + env->spr[SPR_BOOKE_MAS6] =3D sregs.u.e.mas6; > + env->spr[SPR_BOOKE_MAS7] =3D sregs.u.e.mas7_3 >> 32; > + env->spr[SPR_MMUCFG] =3D sregs.u.e.mmucfg; > + env->spr[SPR_BOOKE_TLB0CFG] =3D sregs.u.e.tlbcfg[0]; > + env->spr[SPR_BOOKE_TLB1CFG] =3D sregs.u.e.tlbcfg[1]; > + } > + > + if (sregs.u.e.features & KVM_SREGS_EXP) { > + env->spr[SPR_BOOKE_EPR] =3D sregs.u.e.epr; > + } > + > + if (sregs.u.e.features & KVM_SREGS_E_PD) { > + env->spr[SPR_BOOKE_EPLC] =3D sregs.u.e.eplc; > + env->spr[SPR_BOOKE_EPSC] =3D sregs.u.e.epsc; > + } > + > + if (sregs.u.e.impl_id =3D=3D KVM_SREGS_E_IMPL_FSL) { > + env->spr[SPR_E500_SVR] =3D sregs.u.e.impl.fsl.svr; > + env->spr[SPR_Exxx_MCAR] =3D sregs.u.e.impl.fsl.mcar; > + env->spr[SPR_HID0] =3D sregs.u.e.impl.fsl.hid0; > + > + if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { > + env->spr[SPR_BOOKE_PID1] =3D sregs.u.e.impl.fsl.pid1; > + env->spr[SPR_BOOKE_PID2] =3D sregs.u.e.impl.fsl.pid2; > + } > + } > + > + return 0; > +} > + > +static int kvmppc_get_books_sregs(PowerPCCPU *cpu) > +{ > + CPUPPCState *env =3D &cpu->env; > + struct kvm_sregs sregs; > + int ret; > + int i; > + > + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_SREGS, &sregs); > + if (ret < 0) { > + return ret; > + } > + > + if (!env->external_htab) { > + ppc_store_sdr1(env, sregs.u.s.sdr1); > + } > + > + /* Sync SLB */ > +#ifdef TARGET_PPC64 > + /* > + * The packed SLB array we get from KVM_GET_SREGS only contains > + * information about valid entries. So we flush our internal copy > + * to get rid of stale ones, then put all valid SLB entries back > + * in. > + */ > + memset(env->slb, 0, sizeof(env->slb)); > + for (i =3D 0; i < ARRAY_SIZE(env->slb); i++) { > + target_ulong rb =3D sregs.u.s.ppc64.slb[i].slbe; > + target_ulong rs =3D sregs.u.s.ppc64.slb[i].slbv; > + /* > + * Only restore valid entries > + */ > + if (rb & SLB_ESID_V) { > + ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); > + } > + } > +#endif > + > + /* Sync SRs */ > + for (i =3D 0; i < 16; i++) { > + env->sr[i] =3D sregs.u.s.ppc32.sr[i]; > + } > + > + /* Sync BATs */ > + for (i =3D 0; i < 8; i++) { > + env->DBAT[0][i] =3D sregs.u.s.ppc32.dbat[i] & 0xffffffff; > + env->DBAT[1][i] =3D sregs.u.s.ppc32.dbat[i] >> 32; > + env->IBAT[0][i] =3D sregs.u.s.ppc32.ibat[i] & 0xffffffff; > + env->IBAT[1][i] =3D sregs.u.s.ppc32.ibat[i] >> 32; > + } > + > + return 0; > +} > + > int kvm_arch_get_registers(CPUState *cs) > { > PowerPCCPU *cpu =3D POWERPC_CPU(cs); > CPUPPCState *env =3D &cpu->env; > struct kvm_regs regs; > - struct kvm_sregs sregs; > uint32_t cr; > int i, ret; > =20 > @@ -1059,174 +1251,17 @@ int kvm_arch_get_registers(CPUState *cs) > kvm_get_fp(cs); > =20 > if (cap_booke_sregs) { > - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); > + ret =3D kvmppc_get_booke_sregs(cpu); > if (ret < 0) { > return ret; > } > - > - if (sregs.u.e.features & KVM_SREGS_E_BASE) { > - env->spr[SPR_BOOKE_CSRR0] =3D sregs.u.e.csrr0; > - env->spr[SPR_BOOKE_CSRR1] =3D sregs.u.e.csrr1; > - env->spr[SPR_BOOKE_ESR] =3D sregs.u.e.esr; > - env->spr[SPR_BOOKE_DEAR] =3D sregs.u.e.dear; > - env->spr[SPR_BOOKE_MCSR] =3D sregs.u.e.mcsr; > - env->spr[SPR_BOOKE_TSR] =3D sregs.u.e.tsr; > - env->spr[SPR_BOOKE_TCR] =3D sregs.u.e.tcr; > - env->spr[SPR_DECR] =3D sregs.u.e.dec; > - env->spr[SPR_TBL] =3D sregs.u.e.tb & 0xffffffff; > - env->spr[SPR_TBU] =3D sregs.u.e.tb >> 32; > - env->spr[SPR_VRSAVE] =3D sregs.u.e.vrsave; > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_ARCH206) { > - env->spr[SPR_BOOKE_PIR] =3D sregs.u.e.pir; > - env->spr[SPR_BOOKE_MCSRR0] =3D sregs.u.e.mcsrr0; > - env->spr[SPR_BOOKE_MCSRR1] =3D sregs.u.e.mcsrr1; > - env->spr[SPR_BOOKE_DECAR] =3D sregs.u.e.decar; > - env->spr[SPR_BOOKE_IVPR] =3D sregs.u.e.ivpr; > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_64) { > - env->spr[SPR_BOOKE_EPCR] =3D sregs.u.e.epcr; > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_SPRG8) { > - env->spr[SPR_BOOKE_SPRG8] =3D sregs.u.e.sprg8; > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_IVOR) { > - env->spr[SPR_BOOKE_IVOR0] =3D sregs.u.e.ivor_low[0]; > - kvm_sync_excp(env, POWERPC_EXCP_CRITICAL, SPR_BOOKE_IVOR0); > - env->spr[SPR_BOOKE_IVOR1] =3D sregs.u.e.ivor_low[1]; > - kvm_sync_excp(env, POWERPC_EXCP_MCHECK, SPR_BOOKE_IVOR1); > - env->spr[SPR_BOOKE_IVOR2] =3D sregs.u.e.ivor_low[2]; > - kvm_sync_excp(env, POWERPC_EXCP_DSI, SPR_BOOKE_IVOR2); > - env->spr[SPR_BOOKE_IVOR3] =3D sregs.u.e.ivor_low[3]; > - kvm_sync_excp(env, POWERPC_EXCP_ISI, SPR_BOOKE_IVOR3); > - env->spr[SPR_BOOKE_IVOR4] =3D sregs.u.e.ivor_low[4]; > - kvm_sync_excp(env, POWERPC_EXCP_EXTERNAL, SPR_BOOKE_IVOR4); > - env->spr[SPR_BOOKE_IVOR5] =3D sregs.u.e.ivor_low[5]; > - kvm_sync_excp(env, POWERPC_EXCP_ALIGN, SPR_BOOKE_IVOR5); > - env->spr[SPR_BOOKE_IVOR6] =3D sregs.u.e.ivor_low[6]; > - kvm_sync_excp(env, POWERPC_EXCP_PROGRAM, SPR_BOOKE_IVOR6); > - env->spr[SPR_BOOKE_IVOR7] =3D sregs.u.e.ivor_low[7]; > - kvm_sync_excp(env, POWERPC_EXCP_FPU, SPR_BOOKE_IVOR7); > - env->spr[SPR_BOOKE_IVOR8] =3D sregs.u.e.ivor_low[8]; > - kvm_sync_excp(env, POWERPC_EXCP_SYSCALL, SPR_BOOKE_IVOR8); > - env->spr[SPR_BOOKE_IVOR9] =3D sregs.u.e.ivor_low[9]; > - kvm_sync_excp(env, POWERPC_EXCP_APU, SPR_BOOKE_IVOR9); > - env->spr[SPR_BOOKE_IVOR10] =3D sregs.u.e.ivor_low[10]; > - kvm_sync_excp(env, POWERPC_EXCP_DECR, SPR_BOOKE_IVOR10); > - env->spr[SPR_BOOKE_IVOR11] =3D sregs.u.e.ivor_low[11]; > - kvm_sync_excp(env, POWERPC_EXCP_FIT, SPR_BOOKE_IVOR11); > - env->spr[SPR_BOOKE_IVOR12] =3D sregs.u.e.ivor_low[12]; > - kvm_sync_excp(env, POWERPC_EXCP_WDT, SPR_BOOKE_IVOR12); > - env->spr[SPR_BOOKE_IVOR13] =3D sregs.u.e.ivor_low[13]; > - kvm_sync_excp(env, POWERPC_EXCP_DTLB, SPR_BOOKE_IVOR13); > - env->spr[SPR_BOOKE_IVOR14] =3D sregs.u.e.ivor_low[14]; > - kvm_sync_excp(env, POWERPC_EXCP_ITLB, SPR_BOOKE_IVOR14); > - env->spr[SPR_BOOKE_IVOR15] =3D sregs.u.e.ivor_low[15]; > - kvm_sync_excp(env, POWERPC_EXCP_DEBUG, SPR_BOOKE_IVOR15); > - > - if (sregs.u.e.features & KVM_SREGS_E_SPE) { > - env->spr[SPR_BOOKE_IVOR32] =3D sregs.u.e.ivor_high[0]; > - kvm_sync_excp(env, POWERPC_EXCP_SPEU, SPR_BOOKE_IVOR32); > - env->spr[SPR_BOOKE_IVOR33] =3D sregs.u.e.ivor_high[1]; > - kvm_sync_excp(env, POWERPC_EXCP_EFPDI, SPR_BOOKE_IVOR33= ); > - env->spr[SPR_BOOKE_IVOR34] =3D sregs.u.e.ivor_high[2]; > - kvm_sync_excp(env, POWERPC_EXCP_EFPRI, SPR_BOOKE_IVOR34= ); > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_PM) { > - env->spr[SPR_BOOKE_IVOR35] =3D sregs.u.e.ivor_high[3]; > - kvm_sync_excp(env, POWERPC_EXCP_EPERFM, SPR_BOOKE_IVOR3= 5); > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_PC) { > - env->spr[SPR_BOOKE_IVOR36] =3D sregs.u.e.ivor_high[4]; > - kvm_sync_excp(env, POWERPC_EXCP_DOORI, SPR_BOOKE_IVOR36= ); > - env->spr[SPR_BOOKE_IVOR37] =3D sregs.u.e.ivor_high[5]; > - kvm_sync_excp(env, POWERPC_EXCP_DOORCI, SPR_BOOKE_IVOR37= ); > - } > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_ARCH206_MMU) { > - env->spr[SPR_BOOKE_MAS0] =3D sregs.u.e.mas0; > - env->spr[SPR_BOOKE_MAS1] =3D sregs.u.e.mas1; > - env->spr[SPR_BOOKE_MAS2] =3D sregs.u.e.mas2; > - env->spr[SPR_BOOKE_MAS3] =3D sregs.u.e.mas7_3 & 0xffffffff; > - env->spr[SPR_BOOKE_MAS4] =3D sregs.u.e.mas4; > - env->spr[SPR_BOOKE_MAS6] =3D sregs.u.e.mas6; > - env->spr[SPR_BOOKE_MAS7] =3D sregs.u.e.mas7_3 >> 32; > - env->spr[SPR_MMUCFG] =3D sregs.u.e.mmucfg; > - env->spr[SPR_BOOKE_TLB0CFG] =3D sregs.u.e.tlbcfg[0]; > - env->spr[SPR_BOOKE_TLB1CFG] =3D sregs.u.e.tlbcfg[1]; > - } > - > - if (sregs.u.e.features & KVM_SREGS_EXP) { > - env->spr[SPR_BOOKE_EPR] =3D sregs.u.e.epr; > - } > - > - if (sregs.u.e.features & KVM_SREGS_E_PD) { > - env->spr[SPR_BOOKE_EPLC] =3D sregs.u.e.eplc; > - env->spr[SPR_BOOKE_EPSC] =3D sregs.u.e.epsc; > - } > - > - if (sregs.u.e.impl_id =3D=3D KVM_SREGS_E_IMPL_FSL) { > - env->spr[SPR_E500_SVR] =3D sregs.u.e.impl.fsl.svr; > - env->spr[SPR_Exxx_MCAR] =3D sregs.u.e.impl.fsl.mcar; > - env->spr[SPR_HID0] =3D sregs.u.e.impl.fsl.hid0; > - > - if (sregs.u.e.impl.fsl.features & KVM_SREGS_E_FSL_PIDn) { > - env->spr[SPR_BOOKE_PID1] =3D sregs.u.e.impl.fsl.pid1; > - env->spr[SPR_BOOKE_PID2] =3D sregs.u.e.impl.fsl.pid2; > - } > - } > } > =20 > if (cap_segstate) { > - ret =3D kvm_vcpu_ioctl(cs, KVM_GET_SREGS, &sregs); > + ret =3D kvmppc_get_books_sregs(cpu); > if (ret < 0) { > return ret; > } > - > - if (!env->external_htab) { > - ppc_store_sdr1(env, sregs.u.s.sdr1); > - } > - > - /* Sync SLB */ > -#ifdef TARGET_PPC64 > - /* > - * The packed SLB array we get from KVM_GET_SREGS only contains > - * information about valid entries. So we flush our internal > - * copy to get rid of stale ones, then put all valid SLB entries > - * back in. > - */ > - memset(env->slb, 0, sizeof(env->slb)); > - for (i =3D 0; i < ARRAY_SIZE(env->slb); i++) { > - target_ulong rb =3D sregs.u.s.ppc64.slb[i].slbe; > - target_ulong rs =3D sregs.u.s.ppc64.slb[i].slbv; > - /* > - * Only restore valid entries > - */ > - if (rb & SLB_ESID_V) { > - ppc_store_slb(cpu, rb & 0xfff, rb & ~0xfffULL, rs); > - } > - } > -#endif > - > - /* Sync SRs */ > - for (i =3D 0; i < 16; i++) { > - env->sr[i] =3D sregs.u.s.ppc32.sr[i]; > - } > - > - /* Sync BATs */ > - for (i =3D 0; i < 8; i++) { > - env->DBAT[0][i] =3D sregs.u.s.ppc32.dbat[i] & 0xffffffff; > - env->DBAT[1][i] =3D sregs.u.s.ppc32.dbat[i] >> 32; > - env->IBAT[0][i] =3D sregs.u.s.ppc32.ibat[i] & 0xffffffff; > - env->IBAT[1][i] =3D sregs.u.s.ppc32.ibat[i] >> 32; > - } > } > =20 > if (cap_hior) { --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --oDto3OTLsk6uOlQH Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJW3h6tAAoJEGw4ysog2bOSKJoP/2RwdKoToT5rhL9G+h3zgqao drYbOb+EYB+x1qWhv7dcfExbdKgojplV+y9ontpcPLwag4V27kDDjQDwEL+Sz2tg wg3kLl6m/3HxFU6fd8A2J366afCMVE0ND1sGeEEJ54sXtWG5m6/QFb5smQ9fEAWe JqycL5X0krzGKVILvlzWwqKr3O5XD/MI7DGUh61Hw4w0fo3GElcSzhk4KRweJNfK E99GB/mLDx0f4fBpUMBfgs0cfBqMW5ueCxLBZffjPDoAMi6y4iWpIREI22e9pu7z xHIxH1tGUOi+CR2gC3i/iwS3zEzeLV62Rh9crOD+9bemB6jl3LiMHQFFZ8jWLMGh M4Lbjrj2miKUmGs4fUXtHzMCl9BIS3gE+zEzk1k9MzlojvpbbZt1lz9Eyojm2s3D 8UTvjNLCAa5EMt17gy4KkK9ibJfzTOToUEXv/fovWtrLyPRUlL3QdgkHRud3hbTy QTaMJrZp2A+rxHImJ/N8UVXgppMm/wRSj6sBvns3BU5Ev1gxGGs80UICO8GSuq3Z 9ikCdC5ivxyAMjLou/jr2W1rafT0WXg7MV8LmiHkkYyjldWDwI5MDm72RY50wQnF dlnWtXF37wqj/Dh/Mwyi0u3co7evg2l6pufTAkw2916JnYEZjlfosXKvWOfBOD9f bSe/dXJfBaiw2iSw1jve =yJwd -----END PGP SIGNATURE----- --oDto3OTLsk6uOlQH--