From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:44482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1alPXa-0005Vl-WE for qemu-devel@nongnu.org; Wed, 30 Mar 2016 19:28:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1alPXW-0007Wr-PX for qemu-devel@nongnu.org; Wed, 30 Mar 2016 19:28:46 -0400 Date: Thu, 31 Mar 2016 10:29:45 +1100 From: David Gibson Message-ID: <20160331102945.5a31dbe5@voom.fritz.box> In-Reply-To: <1459357980-29330-1-git-send-email-lvivier@redhat.com> References: <1459357980-29330-1-git-send-email-lvivier@redhat.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; boundary="Sig_/dBlp.q3TN7gZmt1KlLX4uhu"; protocol="application/pgp-signature" Subject: Re: [Qemu-devel] [PATCH] target-ppc: Multiple/String Word alignment exception List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Laurent Vivier Cc: thuth@redhat.com, qemu-ppc@nongnu.org, Alexander Graf , qemu-devel@nongnu.org --Sig_/dBlp.q3TN7gZmt1KlLX4uhu Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable On Wed, 30 Mar 2016 19:13:00 +0200 Laurent Vivier wrote: > If the processor is in little-endian mode, an alignment interrupt must > occur for the following instructions: lmw, stmw, lswi, lswx, stswi or sts= wx. >=20 > This is what happens with KVM, so change TCG to do the same. >=20 > As the instruction can be emulated by the kernel, enable the change > only in softmmu mode. >=20 > Signed-off-by: Laurent Vivier I guess this makes sense given the existing hardware behaviour, even though it seems a bit perverse to me to make the emulator strictly less functional. Alex, what do you think? Note that in time I expect we'll want some new flag to control this behaviour. Given the push towards LE, I think it's pretty likely that future CPUs (maybe even POWER9) will allow these operations on LE without exceptions. I guess one question here is what does the architecture say about this? Does it say these operations will generate alignment exceptions on LE, or just that they may (implementation dependent)? > --- > target-ppc/translate.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 42 insertions(+) >=20 > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 6f0e7b4..e33dcf7 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -3181,6 +3181,13 @@ static void gen_lmw(DisasContext *ctx) > { > TCGv t0; > TCGv_i32 t1; > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > gen_set_access_type(ctx, ACCESS_INT); > /* NIP cannot be restored if the memory exception comes from an help= er */ > gen_update_nip(ctx, ctx->nip - 4); > @@ -3197,6 +3204,13 @@ static void gen_stmw(DisasContext *ctx) > { > TCGv t0; > TCGv_i32 t1; > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > gen_set_access_type(ctx, ACCESS_INT); > /* NIP cannot be restored if the memory exception comes from an help= er */ > gen_update_nip(ctx, ctx->nip - 4); > @@ -3224,6 +3238,13 @@ static void gen_lswi(DisasContext *ctx) > int start =3D rD(ctx->opcode); > int ra =3D rA(ctx->opcode); > int nr; > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > =20 > if (nb =3D=3D 0) > nb =3D 32; > @@ -3252,6 +3273,13 @@ static void gen_lswx(DisasContext *ctx) > { > TCGv t0; > TCGv_i32 t1, t2, t3; > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > gen_set_access_type(ctx, ACCESS_INT); > /* NIP cannot be restored if the memory exception comes from an help= er */ > gen_update_nip(ctx, ctx->nip - 4); > @@ -3273,6 +3301,13 @@ static void gen_stswi(DisasContext *ctx) > TCGv t0; > TCGv_i32 t1, t2; > int nb =3D NB(ctx->opcode); > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > gen_set_access_type(ctx, ACCESS_INT); > /* NIP cannot be restored if the memory exception comes from an help= er */ > gen_update_nip(ctx, ctx->nip - 4); > @@ -3293,6 +3328,13 @@ static void gen_stswx(DisasContext *ctx) > { > TCGv t0; > TCGv_i32 t1, t2; > +#if !defined(CONFIG_USER_ONLY) > + if (ctx->le_mode) { > + gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE= ); > + return; > + } > +#endif > + > gen_set_access_type(ctx, ACCESS_INT); > /* NIP cannot be restored if the memory exception comes from an help= er */ > gen_update_nip(ctx, ctx->nip - 4); > --=20 > 2.5.5 >=20 --=20 David Gibson Senior Software Engineer, Virtualization, Red Hat --Sig_/dBlp.q3TN7gZmt1KlLX4uhu Content-Type: application/pgp-signature Content-Description: OpenPGP digital signature -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJW/GFpAAoJEGw4ysog2bOSJgcP/RSwQLGWB5YKzSYhrIWnafJm eYx77oZCpamLSJ7E0JLtv1d57RLEQMGHA2V++EXfJw78idcfHNGBDCWD6O9hCdb9 DMr8kydt5iZuc2jx7AJDwIvzHw167wLJl28LiJ4NsOMUqIbUZbl0vCKem6GsAy8M egawUJOQwoKHK+rMUWQQT+iHyegg8hCa9sxKae8G74Zg6G7KdkIF3SYUIjaEmtOw 8qdrrRq9dul+YSCab7qsKyC2haO7zC0Oq9C9uMs7C3OpWxRrbvSNVaD8oCV2i/bk hNTcBqZ0Qaxs4sv0fR3Yq/MhRPut5gwFmNWtt2+pXuDoUvfHWjzdB119zzJqYtUz huMN+pzxPflGE+DqOTZkFL0jbteTFp/igcpmihg0rJAXqdf+LAp8/KVoiNa56Wyd zEWYp07DBlC/p8fOVpi6/OhsKdTf6x6vSWSmp+kavLom02Mbh5CW2oaxEi8n3HdY TjJoO0VgKcirWmGI8QoyeCHWVN5Pcqg05gxrnmXYVrAmyO/8SB0KCr8po2Re45pL aRx8haPBEZKop9Mi0/qSYrIDACRE85KoGVl0ePfGgQvyY1BmSl7yxV+EaFyX1x+P VH+HjWSd+oETzoz5+xkI6Iv9ANmE8SR2iJX016eyas8e+1PIEHOefF9Ax8j4syh0 Mww9GdX724tUTLgFySoG =m2cu -----END PGP SIGNATURE----- --Sig_/dBlp.q3TN7gZmt1KlLX4uhu--