From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55325) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am6mV-0006vG-1K for qemu-devel@nongnu.org; Fri, 01 Apr 2016 17:39:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1am6mT-0006Dw-RH for qemu-devel@nongnu.org; Fri, 01 Apr 2016 17:39:02 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:41853) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1am6mT-0006CH-LE for qemu-devel@nongnu.org; Fri, 01 Apr 2016 17:39:01 -0400 Date: Fri, 1 Apr 2016 23:38:48 +0200 From: Aurelien Jarno Message-ID: <20160401213848.GA30783@aurel32.net> References: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1459522179-6584-1-git-send-email-james.hogan@imgtec.com> Subject: Re: [Qemu-devel] [PATCH] tcg/mips: Fix type of tcg_target_reg_alloc_order[] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: James Hogan Cc: qemu-devel@nongnu.org, Richard Henderson On 2016-04-01 15:49, James Hogan wrote: > The MIPS TCG backend is the only one to have > tcg_target_reg_alloc_order[] elements of type TCGReg rather than int. > This resulted in commit 91478cefaaf2 ("tcg: Allocate indirect_base > temporaries in a different order") breaking the build on MIPS since the > type differed from indirect_reg_alloc_order[]: > > tcg/tcg.c:1725:44: error: pointer type mismatch in conditional expression [-Werror] > order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; > ^ > > Make it an array of ints to fix the build and match other architectures. > > Fixes: 91478cefaaf2 ("tcg: Allocate indirect_base temporaries in a different order") > Signed-off-by: James Hogan > Cc: Aurelien Jarno > Cc: Richard Henderson > --- > tcg/mips/tcg-target.inc.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c > index 297bd00910b7..682e19897db0 100644 > --- a/tcg/mips/tcg-target.inc.c > +++ b/tcg/mips/tcg-target.inc.c > @@ -76,7 +76,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { > #define TCG_TMP1 TCG_REG_T9 > > /* check if we really need so many registers :P */ > -static const TCGReg tcg_target_reg_alloc_order[] = { > +static const int tcg_target_reg_alloc_order[] = { > /* Call saved registers. */ > TCG_REG_S0, > TCG_REG_S1, Acked-by: Aurelien Jarno Richard, do you have a pending TCG pull request in which you can include this one? Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net