From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38813) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ar5j7-00077B-9r for qemu-devel@nongnu.org; Fri, 15 Apr 2016 11:32:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ar5j1-0001ni-Lt for qemu-devel@nongnu.org; Fri, 15 Apr 2016 11:32:09 -0400 Received: from mx1.redhat.com ([209.132.183.28]:50362) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1ar5j1-0001nF-H1 for qemu-devel@nongnu.org; Fri, 15 Apr 2016 11:32:03 -0400 Date: Fri, 15 Apr 2016 17:31:58 +0200 From: Radim =?utf-8?B?S3LEjW3DocWZ?= Message-ID: <20160415153158.GC18429@potion.brq.redhat.com> References: <1460691099-3024-1-git-send-email-peterx@redhat.com> <1460691099-3024-13-git-send-email-peterx@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1460691099-3024-13-git-send-email-peterx@redhat.com> Subject: Re: [Qemu-devel] [PATCH v3 12/13] q35: ioapic: add support for split irqchip and irqfd List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Xu Cc: qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, jan.kiszka@web.de, alex.williamson@redhat.com, wexu@redhat.com 2016-04-15 11:31+0800, Peter Xu: > This patch allows Intel IR work with splitted irqchip. Two more fields > are added to IOAPICCommonState to support the translation process (For > future AMD IR support, we will need to provide another AMD-specific > callback for int_remap()). In split irqchip mode, IOAPIC is working in > user space, only update kernel irq routes when entry changed. When IR is > enabled, we directly update the kernel with translated messages. It > works just like a kernel cache for the remapping entries. (Patches are nice, thanks, I'll be looking how to slap EIM on top.) > Since KVM irqfd is using kernel gsi routes to deliver interrupts, as > long as we can support split irqchip, we will support irqfd as > well. Also, since kernel gsi routes will cache translated interrupts, > irqfd delivery will not suffer from any performance impact due to IR. > > And, since we supported irqfd, vhost devices will be able to work > seamlessly with IR now. Logically this should contain both vhost-net and > vhost-user case. Doesn't look that all callers of kvm_irqchip_update_msi_route() are IR aware. I think wrapping the remapping around it might be easiest, kvm_arch_fixup_msi_route() is another candidate. > Here we avoided capturing IOMMU IR invalidation, based on the assumption > that, guest kernel will always first update IR entry, then IOAPIC > entry. As long as guest follows this order to update IOAPIC entries, we > should be safe. The OS configures IOAPIC, MSI and IR independently. e.g. changing the destination LAPIC only updates IRTE and can happen anytime. You have to update kvm_irqchip routes when IRTE changes.