From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47551) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1atfnr-0003IW-4j for qemu-devel@nongnu.org; Fri, 22 Apr 2016 14:27:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1atfnp-00016X-Ud for qemu-devel@nongnu.org; Fri, 22 Apr 2016 14:27:43 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:56581) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1atfnp-00016L-Oe for qemu-devel@nongnu.org; Fri, 22 Apr 2016 14:27:41 -0400 Date: Fri, 22 Apr 2016 20:27:38 +0200 From: Aurelien Jarno Message-ID: <20160422182738.GA25273@aurel32.net> References: <1461341333-19646-1-git-send-email-sergey.fedorov@linaro.org> <1461341333-19646-11-git-send-email-sergey.fedorov@linaro.org> <20160422164743.GA23711@aurel32.net> <20160422165159.GB23711@aurel32.net> <571A58AA.9040502@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <571A58AA.9040502@gmail.com> Subject: Re: [Qemu-devel] [PATCH v2 10/11] tcg/mips: Make direct jump patching thread-safe List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sergey Fedorov Cc: Sergey Fedorov , qemu-devel@nongnu.org, Alex =?iso-8859-15?Q?Benn=E9e?= , Paolo Bonzini , Peter Crosthwaite , Richard Henderson On 2016-04-22 20:00, Sergey Fedorov wrote: > On 22/04/16 19:51, Aurelien Jarno wrote: > > On 2016-04-22 18:47, Aurelien Jarno wrote: > >> On 2016-04-22 19:08, Sergey Fedorov wrote: > >>> From: Sergey Fedorov > >>> > >>> Ensure direct jump patching in MIPS is atomic by using > >>> atomic_read()/atomic_set() for code patching. > >>> > >>> Signed-off-by: Sergey Fedorov > >>> Signed-off-by: Sergey Fedorov > >>> --- > >>> > >>> Changes in v2: > >>> * s/atomic_write/atomic_set/ > >>> > >>> tcg/mips/tcg-target.inc.c | 3 ++- > >>> 1 file changed, 2 insertions(+), 1 deletion(-) > >>> > >>> diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c > >>> index 682e19897db0..cefc0398018a 100644 > >>> --- a/tcg/mips/tcg-target.inc.c > >>> +++ b/tcg/mips/tcg-target.inc.c > >>> @@ -1886,6 +1886,7 @@ static void tcg_target_init(TCGContext *s) > >>> void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) > >>> { > >>> uint32_t *ptr = (uint32_t *)jmp_addr; > >>> - *ptr = deposit32(*ptr, 0, 26, addr >> 2); > >>> + uint32_t insn = atomic_read(ptr); > >>> + atomic_set(ptr, deposit32(insn, 0, 26, addr >> 2)); > >>> flush_icache_range(jmp_addr, jmp_addr + 4); > >> Does it really make sense to read and write the value atomically? The > >> resulting operation is still not atomic, something can happen in > >> between. > > Hmm, thinking more about that, given the only instruction used is "J", > > we don't have to read the value, patch it and write it. We can directly > > use something like (untested): > > > > atomic_set(ptr, (0x02 << 26) | (addr >> 2)); > > Hmm, looking at "case INDEX_op_goto_tb:" in tcg_out_op() again I'm > thinking about: > > atomic_set(ptr, deposit32(OPC_J, 0, 26, addr >> 2)); Oh right, I forgot when reviewing the patch that this code is actually in tcg-target.inc.c, and that the OPC_J constant is available. Your version looks good to me. Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net