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From: Andrew Jones <drjones@redhat.com>
To: Shannon Zhao <shannon.zhao@linaro.org>
Cc: Shannon Zhao <zhaoshenglong@huawei.com>,
	qemu-arm@nongnu.org, peter.maydell@linaro.org,
	qemu-devel@nongnu.org, peter.huangpeng@huawei.com
Subject: Re: [Qemu-devel] [PATCH v3 2/3] hw/arm/virt: Add PMU node for virt machine
Date: Mon, 25 Apr 2016 16:17:42 +0200	[thread overview]
Message-ID: <20160425141742.37d774ucb4qz7nx7@hawk.localdomain> (raw)
In-Reply-To: <571E21AA.5000503@linaro.org>

On Mon, Apr 25, 2016 at 09:54:50PM +0800, Shannon Zhao wrote:
> On 2016年04月25日 19:52, Andrew Jones wrote:
> > On Mon, Apr 25, 2016 at 07:37:13PM +0800, Shannon Zhao wrote:
> >> > 
> >> > 
> >> > On 2016/4/25 17:22, Andrew Jones wrote:
> >>> > > On Mon, Apr 25, 2016 at 03:11:45PM +0800, Shannon Zhao wrote:
> >>>>> > >> > From: Shannon Zhao <shannon.zhao@linaro.org>
> >>>>> > >> > 
> >>>>> > >> > Add a virtual PMU device for virt machine while use PPI 7 for PMU
> >>>>> > >> > overflow interrupt number.
> >>>>> > >> > 
> >>>>> > >> > Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
> >>>>> > >> > ---
> >>>>> > >> >  hw/arm/virt.c         | 34 ++++++++++++++++++++++++++++++++++
> >>>>> > >> >  include/hw/arm/virt.h |  4 ++++
> >>>>> > >> >  include/sysemu/kvm.h  |  1 +
> >>>>> > >> >  stubs/kvm.c           |  5 +++++
> >>>>> > >> >  target-arm/kvm64.c    | 39 +++++++++++++++++++++++++++++++++++++++
> >>>>> > >> >  5 files changed, 83 insertions(+)
> >>>>> > >> > 
> >>>>> > >> > diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> >>>>> > >> > index 56d35c7..c3632d8 100644
> >>>>> > >> > --- a/hw/arm/virt.c
> >>>>> > >> > +++ b/hw/arm/virt.c
> >>>>> > >> > @@ -428,6 +428,38 @@ static void fdt_add_gic_node(VirtBoardInfo *vbi, int type)
> >>>>> > >> >      qemu_fdt_setprop_cell(vbi->fdt, "/intc", "phandle", vbi->gic_phandle);
> >>>>> > >> >  }
> >>>>> > >> >  
> >>>>> > >> > +static void fdt_add_pmu_nodes(const VirtBoardInfo *vbi, int gictype)
> >>>>> > >> > +{
> >>>>> > >> > +    CPUState *cpu;
> >>>>> > >> > +    ARMCPU *armcpu;
> >>>>> > >> > +    uint32_t irqflags = GIC_FDT_IRQ_FLAGS_LEVEL_HI;
> >>>>> > >> > +
> >>>>> > >> > +    CPU_FOREACH(cpu) {
> >>>>> > >> > +        armcpu = ARM_CPU(cpu);
> >>>>> > >> > +        if (!armcpu->has_pmu) {
> >>>>> > >> > +            return;
> >>>>> > >> > +        }
> >>>>> > >> > +
> >>>>> > >> > +        kvm_arm_pmu_create(cpu, PPI(VIRTUAL_PMU_IRQ));
> >>> > > I think we need to return a failure code from kvm_arm_pmu_create, and
> >>> > > then do
> >>> > > 
> >>> > >            if (!kvm_arm_pmu_create(...)) {
> >>> > >                return;
> >>> > >            }
> >>> > > 
> >>> > > Otherwise we create a /pmu node for the guest that won't work.
> >>> > > 
> >> > Ok, will update.
> >> > 
> >>>>> > >> > +    }
> >>>>> > >> > +
> >>>>> > >> > +    if (gictype == 2) {
> >>>>> > >> > +        irqflags = deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
> >>>>> > >> > +                             GIC_FDT_IRQ_PPI_CPU_WIDTH,
> >>>>> > >> > +                             (1 << vbi->smp_cpus) - 1);
> >>> > > So, if we're using gicv3, then we're level triggered and these cpu
> >>> > > mask bits aren't defined by the arm,gic-v3.txt bindings spec. Good.
> >>> > > 
> >>> > > If we're using gicv2, then we're edge triggered and this mask is
> >>> > > defined. Assuming the GIC implementation requires using edge
> >>> > > triggered interrupts (as the comment in fdt_add_timer_nodes says),
> >>> > > then OK.
> >>> > > 
> >> > IIRC the comments in fdt_add_timer_nodes are not correct now since KVM
> >> > makes PPI level triggered.
> >> > 
> >> >     /* Note that on A15 h/w these interrupts are level-triggered,
> >> >      * but for the GIC implementation provided by both QEMU and KVM
> >> >      * they are edge-triggered.
> >> >      */
> > OK, in that case the comment should be updated to say something like
> > "used to", but I suspect it's too late for the timer to switch to
> > level at this point anyway, unless KVM can be probed to determine if
> > level is OK.
> > 
> > However, for PMU, we know that if the PMU feature exists, then level is
> > OK, so if we want a level triggered interrupt for PMU, then we should
> > change the giv2 irqflags assignment to an '|=' of the cpu mask.
> Since for gicv2, the maximum of vbi->smp_cpus is 8, so it will not
> overflow and the result of deposit32 is right, I think.

Yes. I was actually referring to the level flag, thinking it was getting
overwritten with zero, but now I see in deposit32's description that
"Bits of @value outside the bit field are not modified." So this is
fine.

Thanks,
drew

  reply	other threads:[~2016-04-25 14:18 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-25  7:11 [Qemu-devel] [PATCH v3 0/3] Add guest PMU in machine virt Shannon Zhao
2016-04-25  7:11 ` [Qemu-devel] [PATCH v3 1/3] target-arm: kvm64: set guest PMUv3 feature bit if supported Shannon Zhao
2016-04-25  7:11 ` [Qemu-devel] [PATCH v3 2/3] hw/arm/virt: Add PMU node for virt machine Shannon Zhao
2016-04-25  9:22   ` Andrew Jones
2016-04-25 11:37     ` Shannon Zhao
2016-04-25 11:52       ` Andrew Jones
2016-04-25 13:54         ` Shannon Zhao
2016-04-25 14:17           ` Andrew Jones [this message]
2016-04-25  7:11 ` [Qemu-devel] [PATCH v3 3/3] hw/arm/virt-acpi-build: Add PMU IRQ number in ACPI table Shannon Zhao
2016-04-25 12:42   ` Andrew Jones
2016-04-25 13:49     ` Shannon Zhao
2016-04-26 11:08       ` Shannon Zhao
2016-04-26 11:18         ` Andrew Jones

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