From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53478) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avgxu-0005Ua-RH for qemu-devel@nongnu.org; Thu, 28 Apr 2016 04:06:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1avgxp-00058c-Rt for qemu-devel@nongnu.org; Thu, 28 Apr 2016 04:06:26 -0400 Received: from mx1.redhat.com ([209.132.183.28]:60667) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1avgxp-00058S-Jz for qemu-devel@nongnu.org; Thu, 28 Apr 2016 04:06:21 -0400 Date: Thu, 28 Apr 2016 16:06:15 +0800 From: Peter Xu Message-ID: <20160428080615.GE20143@pxdev.xzpeter.org> References: <1461827144-6937-1-git-send-email-peterx@redhat.com> <1461827144-6937-11-git-send-email-peterx@redhat.com> <5721BC81.9070708@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <5721BC81.9070708@web.de> Subject: Re: [Qemu-devel] [PATCH v5 10/18] intel_iommu: Add support for PCI MSI remap List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: qemu-devel@nongnu.org, imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, marcel@redhat.com, mst@redhat.com, pbonzini@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On Thu, Apr 28, 2016 at 09:32:17AM +0200, Jan Kiszka wrote: > On 2016-04-28 09:05, Peter Xu wrote: > > This patch enables interrupt remapping for PCI devices. > > > > To play the trick, one memory region "iommu_ir" is added as child region > > of the original iommu memory region, covering range 0xfeeXXXXX (which is > > the address range for APIC). All the writes to this range will be taken > > as MSI, and translation is carried out only when IR is enabled. > > > > Idea suggested by Paolo Bonzini. > > This still lacks source (device ID) identification, right? Were did the > memory write attribute thing go? Given that you actually introduce a > separate MSI target address space for the IOAPIC (btw, once there will > be more than one instance, like on real hw today) and that you will need > yet another one for each HPET, why not address this with a common scheme > now, ie. by transmitting the source ID along the write via that attribute? Yes, it still lacks verification for SID. Currently there are two ways to implement it. One is to use MemAttrs and provide write_with_attrs() rather than write(). The other one is to keep using write(), but instead passing in VTDAddressSpace rather than IntelIOMMUState when init each IR memory region: ----------------- diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7122e5b..6493093 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2205,6 +2205,9 @@ static void vtd_mem_ir_write(void *opaque, hwaddr addr, int ret = 0; MSIMessage from = {0}, to = {0}; + VTDAddressSpace *as = opaque; + /* Do whatever we want using as->bus and as->devfn... */ + from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST; from.data = (uint32_t) value; @@ -2276,7 +2279,7 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn) memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s), &s->iommu_ops, "intel_iommu", UINT64_MAX); memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s), - &vtd_mem_ir_ops, s, "intel_iommu_ir", + &vtd_mem_ir_ops, vtd_dev_as, "intel_iommu_ir", VTD_INTERRUPT_ADDR_SIZE); memory_region_add_subregion(&vtd_dev_as->iommu, VTD_INTERRUPT_ADDR_FIRST, &vtd_dev_as->iommu_ir); ----------------- If to use the above method, we'll need no scheme change. But now since MemAttrs is ready (it's ready, right?), maybe I should start to use it, which is the standard way to do. Thanks to point out. Will make the change in v6. -- peterx