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From: James Hogan <james.hogan@imgtec.com>
To: Leon Alrae <leon.alrae@imgtec.com>
Cc: qemu-devel@nongnu.org, Yongbok Kim <yongbok.kim@imgtec.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Peter Maydell <peter.maydell@linaro.org>
Subject: Re: [Qemu-devel] [PATCH] target-mips: Fix RDHWR exception host PC
Date: Thu, 28 Apr 2016 10:01:42 +0100	[thread overview]
Message-ID: <20160428090142.GE19902@jhogan-linux.le.imgtec.org> (raw)
In-Reply-To: <5721CF70.2010801@imgtec.com>

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On Thu, Apr 28, 2016 at 09:53:04AM +0100, Leon Alrae wrote:
> On 27/04/16 23:21, James Hogan wrote:
> > Commit b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> > changed the rdhwr helpers to use check_hwrena() to check the register
> > being accessed is enabled in CP0_HWREna when used from user mode. If
> > that check fails an EXCP_RI exception is raised at the host PC
> > calculated with GETPC().
> > 
> > However check_hwrena() may not be fully inlined as the
> > do_raise_exception() part of it is common regardless of the arguments.
> > This causes GETPC() to calculate the address in the call in the helper
> > instead of the generated code calling the helper. No TB will be found
> > and the EPC reported with the resulting guest RI exception points to the
> > beginning of the TB instead of the RDHWR instruction.
> > 
> > We can't reliably force check_hwrena() to be inlined, and converting it
> > to a macro would be ugly, so instead pass the host PC in as an argument,
> > with each rdhwr helper passing GETPC(). This should avoid any dependence
> > on compiler behaviour, and in practice seems to prevent the partial
> > inlining of check_hwrena() on x86_64.

Note also this sentence isn't actually very clear. preventing partial
inlining sounds like it stops inlining altogether, whereas actually I
meant that it seems to ensure full inlining of check_hwrena(). Perhaps
you could change it to ", and in practice seems to ensure the full
inlining of check_hwrena() on x86_64." when you apply it.

> > 
> > This issue causes failures when running a MIPS KVM (trap & emulate)
> > guest in a MIPS QEMU TCG guest, as the inner guest kernel will do a
> > RDHWR of counter, which is disabled in the outer guest's CP0_HWREna by
> > KVM so it can emulate the inner guest's counter. The emulation fails and
> > the RI exception is passed to the inner guest.
> > 
> > Fixes: b00c72180c36 ("target-mips: add PC, XNP reg numbers to RDHWR")
> > Signed-off-by: James Hogan <james.hogan@imgtec.com>
> > Cc: Leon Alrae <leon.alrae@imgtec.com>
> > Cc: Yongbok Kim <yongbok.kim@imgtec.com>
> > Cc: Aurelien Jarno <aurelien@aurel32.net>
> > ---
> >  target-mips/op_helper.c | 16 ++++++++--------
> >  1 file changed, 8 insertions(+), 8 deletions(-)
> 
> Whoops, thanks for the fix. I'll send the pullreq soon, hopefully it's
> not too late for 2.6.

Thanks

James

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      reply	other threads:[~2016-04-28  9:01 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-04-27 22:21 [Qemu-devel] [PATCH] target-mips: Fix RDHWR exception host PC James Hogan
2016-04-28  8:51 ` Aurelien Jarno
2016-04-28  8:55   ` James Hogan
2016-04-28  8:53 ` Leon Alrae
2016-04-28  9:01   ` James Hogan [this message]

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