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Date: Thu, 12 May 2016 19:25:58 +0200
From: Radim =?utf-8?B?S3LEjW3DocWZ?= <rkrcmar@redhat.com>
Message-ID: <20160512172557.GA28226@potion>
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Subject: Re: [Qemu-devel] [PATCH v2] target-i386: implement CPUID[0xB]
 (Extended Topology Enumeration)
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To: qemu-devel@nongnu.org
Cc: Paolo Bonzini <pbonzini@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Richard Henderson <rth@twiddle.net>

2016-05-12 19:15+0200, Radim Kr=C4=8Dm=C3=A1=C5=99:
> I looked at a dozen Intel CPU that have this CPUID and all of them
> always had Core offset as 1 (a wasted bit when hyperthreading is
> disabled) and Package offset at least 4 (wasted bits at <=3D 4 cores).
>=20
> QEMU uses more compact IDs and it doesn't make much sense to change it
> now.  I keep the SMT and Core sub-leaves even if there is just one
> thread/core;  it makes the code simpler and there should be no harm.
>=20
> Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 <rkrcmar@redhat.com>
> ---
> diff --git a/target-i386/cpu.c b/target-i386/cpu.c
> @@ -35,6 +35,7 @@
> @@ -2460,6 +2461,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t in=
dex, uint32_t count,
>              *edx =3D 0;
>          }
>          break;
> +    case 0xB:
> +        /* Extended Topology Enumeration Leaf */
> +        if (!cpu->enable_cpuid_0xb) {
> +                *eax =3D *ebx =3D *ecx =3D *edx =3D 0;
> +                break;
> +        }
> +
> +        *ecx =3D count & 0xff;
> +        *edx =3D cpu->apic_id;
> +
> +        switch (*ecx) {

I missed *ecx -> count from v1 reviews.  Sending v3, sorry.