From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:60850) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b19Sf-0006Y5-6j for qemu-devel@nongnu.org; Fri, 13 May 2016 05:32:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b19Sb-00005w-Mv for qemu-devel@nongnu.org; Fri, 13 May 2016 05:32:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:59712) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b19Sb-00005o-Ek for qemu-devel@nongnu.org; Fri, 13 May 2016 05:32:41 -0400 Date: Fri, 13 May 2016 11:32:38 +0200 From: Igor Mammedov Message-ID: <20160513113238.30f9917f@nial.brq.redhat.com> In-Reply-To: <1463073866-28802-1-git-send-email-rkrcmar@redhat.com> References: <1463073866-28802-1-git-send-email-rkrcmar@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3] target-i386: implement CPUID[0xB] (Extended Topology Enumeration) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Radim =?UTF-8?B?S3LEjW3DocWZ?= Cc: qemu-devel@nongnu.org, Paolo Bonzini , Eduardo Habkost , Richard Henderson On Thu, 12 May 2016 19:24:26 +0200 Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: > I looked at a dozen Intel CPU that have this CPUID and all of them > always had Core offset as 1 (a wasted bit when hyperthreading is > disabled) and Package offset at least 4 (wasted bits at <=3D 4 cores). >=20 > QEMU uses more compact IDs and it doesn't make much sense to change it > now. I keep the SMT and Core sub-leaves even if there is just one > thread/core; it makes the code simpler and there should be no harm. >=20 > Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 Reviewed-by: Igor Mammedov > --- > This patch depends on Igor's "pc: add 2.7 machine". >=20 > v2: > * assert *eax instead of silently masking [Eduardo] > * backward compatibility through CPU property [Eduardo] >=20 > v3: use count instead of *ecx to access leaves, hardware does >=20 > include/hw/i386/pc.h | 7 ++++++- > target-i386/cpu-qom.h | 3 +++ > target-i386/cpu.c | 32 ++++++++++++++++++++++++++++++++ > target-i386/cpu.h | 5 +++++ > 4 files changed, 46 insertions(+), 1 deletion(-) >=20 > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h > index a91e8e734f07..e294fa945d30 100644 > --- a/include/hw/i386/pc.h > +++ b/include/hw/i386/pc.h > @@ -361,7 +361,12 @@ int e820_get_num_entries(void); > bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); > =20 > #define PC_COMPAT_2_6 \ > - HW_COMPAT_2_6 > + HW_COMPAT_2_6 \ > + {\ > + .driver =3D TYPE_X86_CPU,\ > + .property =3D "cpuid-0xb",\ > + .value =3D "off",\ > + }, > =20 > #define PC_COMPAT_2_5 \ > PC_COMPAT_2_6 \ > diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h > index cb750176c0c0..b84963d42463 100644 > --- a/target-i386/cpu-qom.h > +++ b/target-i386/cpu-qom.h > @@ -115,6 +115,9 @@ typedef struct X86CPU { > */ > bool enable_pmu; > =20 > + /* Compatibility bits for old machine types. */ > + bool enable_cpuid_0xb; > + > /* in order to simplify APIC support, we leave this pointer to the > user */ > struct DeviceState *apic_state; > diff --git a/target-i386/cpu.c b/target-i386/cpu.c > index d0b5b691563c..a17ef191c270 100644 > --- a/target-i386/cpu.c > +++ b/target-i386/cpu.c > @@ -35,6 +35,7 @@ > #include "sysemu/arch_init.h" > =20 > #include "hw/hw.h" > +#include "hw/i386/topology.h" > #if defined(CONFIG_KVM) > #include > #endif > @@ -2460,6 +2461,36 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t inde= x, uint32_t count, > *edx =3D 0; > } > break; > + case 0xB: > + /* Extended Topology Enumeration Leaf */ > + if (!cpu->enable_cpuid_0xb) { > + *eax =3D *ebx =3D *ecx =3D *edx =3D 0; > + break; > + } > + > + *ecx =3D count & 0xff; > + *edx =3D cpu->apic_id; > + > + switch (count) { > + case 0: > + *eax =3D apicid_core_offset(smp_cores, smp_threads); > + *ebx =3D smp_threads; > + *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; > + break; > + case 1: > + *eax =3D apicid_pkg_offset(smp_cores, smp_threads); > + *ebx =3D smp_cores * smp_threads; > + *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; > + break; > + default: > + *eax =3D 0; > + *ebx =3D 0; > + *ecx |=3D CPUID_TOPOLOGY_LEVEL_INVALID; > + } > + > + assert(!(*eax & ~0x1f)); > + *ebx &=3D 0xffff; /* The count doesn't need to be reliable. */ > + break; > case 0xD: { > KVMState *s =3D cs->kvm_state; > uint64_t ena_mask; > @@ -3221,6 +3252,7 @@ static Property x86_cpu_properties[] =3D { > DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), > DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), > DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), > + DEFINE_PROP_BOOL("cpuid-0xb", X86CPU, enable_cpuid_0xb, true), > DEFINE_PROP_END_OF_LIST() > }; > =20 > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > index 732eb6d7ec79..b460c2debc1c 100644 > --- a/target-i386/cpu.h > +++ b/target-i386/cpu.h > @@ -635,6 +635,11 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; > #define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability = */ > #define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ > =20 > +/* CPUID[0xB].ECX level types */ > +#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8) > +#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8) > +#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8) > + > #ifndef HYPERV_SPINLOCK_NEVER_RETRY > #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF > #endif