From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:59736) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2DpF-00073N-Ct for qemu-devel@nongnu.org; Mon, 16 May 2016 04:24:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b2DpA-0005Hz-Ak for qemu-devel@nongnu.org; Mon, 16 May 2016 04:24:29 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46418) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b2DpA-0005Hd-60 for qemu-devel@nongnu.org; Mon, 16 May 2016 04:24:24 -0400 Received: from int-mx14.intmail.prod.int.phx2.redhat.com (int-mx14.intmail.prod.int.phx2.redhat.com [10.5.11.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id E65697F6A5 for ; Mon, 16 May 2016 08:24:22 +0000 (UTC) Date: Mon, 16 May 2016 10:24:19 +0200 From: Igor Mammedov Message-ID: <20160516102419.43e4b016@nial.brq.redhat.com> In-Reply-To: <1463340214-8721-3-git-send-email-marcel@redhat.com> References: <1463340214-8721-1-git-send-email-marcel@redhat.com> <1463340214-8721-3-git-send-email-marcel@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH V2 2/4] pci: reserve 64 bit MMIO range for PCI hotplug List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Marcel Apfelbaum Cc: qemu-devel@nongnu.org, mst@redhat.com, lersek@redhat.com, ehabkost@redhat.com On Sun, 15 May 2016 22:23:32 +0300 Marcel Apfelbaum wrote: > Using the firmware assigned MMIO ranges for 64-bit PCI window > leads to zero space for hot-plugging PCI devices over 4G. > > PC machines can use the whole CPU addressable range after > the space reserved for memory-hotplug. > > Signed-off-by: Marcel Apfelbaum > --- > hw/pci/pci.c | 16 ++++++++++++++-- > 1 file changed, 14 insertions(+), 2 deletions(-) > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > index bb605ef..44dd949 100644 > --- a/hw/pci/pci.c > +++ b/hw/pci/pci.c > @@ -41,6 +41,7 @@ > #include "hw/hotplug.h" > #include "hw/boards.h" > #include "qemu/cutils.h" > +#include "hw/i386/pc.h" > > //#define DEBUG_PCI > #ifdef DEBUG_PCI > @@ -2467,8 +2468,19 @@ static void pci_dev_get_w64(PCIBus *b, PCIDevice *dev, void *opaque) > > void pci_bus_get_w64_range(PCIBus *bus, Range *range) > { > - range->begin = range->end = 0; > - pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); > + Object *machine = qdev_get_machine(); > + if (object_dynamic_cast(machine, TYPE_PC_MACHINE)) { > + PCMachineState *pcms = PC_MACHINE(machine); > + range->begin = pc_machine_get_reserved_memory_end(pcms); that line should break linking on other targets which don't have pc_machine_get_reserved_memory_end() probably for got to add stub. > + if (!range->begin) { > + range->begin = ROUND_UP(0x100000000ULL + pcms->above_4g_mem_size, > + 1ULL << 30); > + } > + range->end = 1ULL << 40; /* 40 bits physical */ x86 specific in generic code ARM also has 64-bit PCI MMIO /git grep VIRT_PCIE_MMIO_HIGH/ perhaps range should be a property of PCI bus, where a board sets its own values for start/size > + } else { > + range->begin = range->end = 0; > + pci_for_each_device_under_bus(bus, pci_dev_get_w64, range); > + } > } > > static bool pcie_has_upstream_port(PCIDevice *dev)