From: Pranith Kumar <bobby.prani@gmail.com>
To: "Peter Maydell" <peter.maydell@linaro.org>,
"Richard Henderson" <rth@twiddle.net>,
"Alex Bennée" <alex.bennee@linaro.org>,
"Sergey Fedorov" <serge.fdrv@gmail.com>,
"open list:ARM" <qemu-arm@nongnu.org>,
"open list:All patches CC here" <qemu-devel@nongnu.org>
Subject: [Qemu-devel] [RFC PATCH 3/3] tcg: Add frontend support for fence gen in ARMv7
Date: Tue, 24 May 2016 13:18:56 -0400 [thread overview]
Message-ID: <20160524171856.1000-4-bobby.prani@gmail.com> (raw)
In-Reply-To: <20160524171856.1000-1-bobby.prani@gmail.com>
Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
---
target-arm/translate.c | 11 +++++++++--
tcg/tcg-op.h | 5 +++++
tcg/tcg-opc.h | 2 +-
3 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/target-arm/translate.c b/target-arm/translate.c
index c946c0e..3407176 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -7980,9 +7980,13 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
gen_clrex(s);
return;
case 4: /* dsb */
+ ARCH(7);
+ return;
case 5: /* dmb */
ARCH(7);
- /* We don't emulate caches so these are a no-op. */
+ if (TCG_TARGET_HAS_fence) {
+ tcg_gen_fence();
+ }
return;
case 6: /* isb */
/* We need to break the TB after this insn to execute
@@ -10330,8 +10334,11 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_clrex(s);
break;
case 4: /* dsb */
+ break;
case 5: /* dmb */
- /* These execute as NOPs. */
+ if (TCG_TARGET_HAS_fence) {
+ tcg_gen_fence();
+ }
break;
case 6: /* isb */
/* We need to break the TB after this insn
diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index c446d3d..1c7e8fc 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -261,6 +261,11 @@ static inline void tcg_gen_br(TCGLabel *l)
tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
}
+static inline void tcg_gen_fence(void)
+{
+ tcg_gen_op1(&tcg_ctx, INDEX_op_fence, 0);
+}
+
/* Helper calls. */
/* 32 bit ops */
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index b772d90..4696cf1 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -42,7 +42,7 @@ DEF(br, 0, 0, 1, TCG_OPF_BB_END)
# define IMPL64 TCG_OPF_64BIT
#endif
-DEF(fence, 0, 0, 0, TCG_OPF_SIDE_EFFECTS)
+DEF(fence, 0, 0, 0, 0)
DEF(mov_i32, 1, 1, 0, TCG_OPF_NOT_PRESENT)
DEF(movi_i32, 1, 0, 1, TCG_OPF_NOT_PRESENT)
--
2.8.3
next prev parent reply other threads:[~2016-05-24 17:19 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20160524171856.1000-1-bobby.prani@gmail.com>
2016-05-24 17:18 ` [Qemu-devel] [RFC PATCH 1/3] Introduce TCGOpcode for fence instruction Pranith Kumar
2016-05-24 17:32 ` Peter Maydell
2016-05-24 18:05 ` Pranith Kumar
2016-05-24 17:18 ` [Qemu-devel] [RFC PATCH 2/3] tcg: Add support for fence generation in x86 backend Pranith Kumar
2016-05-25 17:35 ` Richard Henderson
2016-05-25 19:25 ` Alex Bennée
2016-05-25 19:43 ` Sergey Fedorov
2016-05-25 19:59 ` Pranith Kumar
2016-05-25 20:02 ` Sergey Fedorov
2016-05-25 19:50 ` Richard Henderson
2016-05-25 19:57 ` Pranith Kumar
2016-05-25 19:56 ` Pranith Kumar
2016-05-26 16:09 ` Alex Bennée
2016-05-24 17:18 ` Pranith Kumar [this message]
2016-05-25 17:36 ` [Qemu-devel] [RFC PATCH 3/3] tcg: Add frontend support for fence gen in ARMv7 Richard Henderson
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