[Qemu-devel] [RFC 05/10] target-arm: End TB after ldrex instruction

[Alvise Rigo <a.rigo@virtualopensystems.com>]

A VCPU executing a ldrex instruction might query flushes to other VCPUs:
in this cases, the calling VCPU uses cpu_exit to exit from the cpu loop
and wait the other VCPUs to perform the flush. In order to exit from the
cpu loop as soon as possible, interrupt the TB after the ldrex
instruction.

Signed-off-by: Alvise Rigo <a.rigo@virtualopensystems.com>
---
 target-arm/translate-a64.c | 2 ++
 target-arm/translate.c     | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 376cb1c..2a14c14 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1875,6 +1875,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn)
         if (!is_store) {
             s->is_ldex = true;
             gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair);
+            gen_a64_set_pc_im(s->pc);
+            s->is_jmp = DISAS_JUMP;
         } else {
             gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair);
         }
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 0677e04..7c1cb19 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -8807,6 +8807,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)
                             default:
                                 abort();
                             }
+                            gen_set_pc_im(s, s->pc);
+                            s->is_jmp = DISAS_JUMP;
                         } else {
                             rm = insn & 0xf;
                             switch (op1) {
-- 
2.8.3