From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33469) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7ILA-0000hh-JH for qemu-devel@nongnu.org; Mon, 30 May 2016 04:14:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7IL4-0004qk-JQ for qemu-devel@nongnu.org; Mon, 30 May 2016 04:14:23 -0400 Received: from mx1.redhat.com ([209.132.183.28]:46245) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7IL4-0004qd-Dq for qemu-devel@nongnu.org; Mon, 30 May 2016 04:14:18 -0400 Date: Mon, 30 May 2016 16:14:09 +0800 From: Peter Xu Message-ID: <20160530081409.GC6656@pxdev.xzpeter.org> References: <1463469353-25642-1-git-send-email-peterx@redhat.com> <1463469353-25642-8-git-send-email-peterx@redhat.com> <20160530054509.GB6656@pxdev.xzpeter.org> <574BD600.4040601@web.de> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <574BD600.4040601@web.de> Subject: Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Jan Kiszka Cc: David Kiarie , QEMU Developers , imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com, jasowang@redhat.com, Marcel Apfelbaum , "Michael S. Tsirkin" , pbonzini@redhat.com, rkrcmar@redhat.com, alex.williamson@redhat.com, wexu@redhat.com On Mon, May 30, 2016 at 07:56:16AM +0200, Jan Kiszka wrote: > On 2016-05-30 07:45, Peter Xu wrote: > > On Sun, May 29, 2016 at 11:21:35AM +0300, David Kiarie wrote: > > [...] > >>>> + > >>>> +/* Programming format for MSI/MSI-X addresses */ > >>>> +union VTD_IR_MSIAddress { > >>>> + struct { > >>>> + uint8_t __not_care:2; > >>>> + uint8_t index_h:1; /* Interrupt index bit 15 */ > >>>> + uint8_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ > >>>> + uint8_t int_mode:1; /* Interrupt format */ > >>>> + uint16_t index_l:15; /* Interrupt index bit 14-0 */ > >>>> + uint16_t __head:12; /* Should always be: 0x0fee */ > >>>> + } QEMU_PACKED; > >>>> + uint32_t data; > >>>> +}; > >>> > >>> In a recent discussion, it was brought to my attention that you might > >>> have a problem with bitfields when the host cpu is not x86. Have you > >>> considered this ? > >> > >> In a case when say the host cpu is little endian. > > > > I assume you mean when host cpu is big endian. x86 was little endian, > > and I was testing on x86. > > > > I think you are right. I should do conditional byte swap for all > > uint{16/32/64} cases within the fields. For example, index_l field in > > above VTD_IR_MSIAddress. And there are several other cases that need > > special treatment in the patchset. Will go over and fix corresponding > > issues in next version. > > You actually need bit-swap with bit fields, see e.g. hw/net/vmxnet3.h. Not noticed about bit-field ordering before... So maybe I need both? Thanks, -- peterx