From: Peter Xu <peterx@redhat.com>
To: David Kiarie <davidkiarie4@gmail.com>
Cc: Jan Kiszka <jan.kiszka@web.de>,
QEMU Developers <qemu-devel@nongnu.org>,
imammedo@redhat.com, rth@twiddle.net, ehabkost@redhat.com,
jasowang@redhat.com, Marcel Apfelbaum <marcel@redhat.com>,
"Michael S. Tsirkin" <mst@redhat.com>,
pbonzini@redhat.com, rkrcmar@redhat.com,
alex.williamson@redhat.com, wexu@redhat.com
Subject: Re: [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR
Date: Mon, 30 May 2016 17:16:49 +0800 [thread overview]
Message-ID: <20160530091649.GD6656@pxdev.xzpeter.org> (raw)
In-Reply-To: <CABdVeAAesomLDq5Yd0HT=SmmMu4N9uKYpVGy5Yn0BRMDNK6ycQ@mail.gmail.com>
On Mon, May 30, 2016 at 11:54:52AM +0300, David Kiarie wrote:
> On Mon, May 30, 2016 at 11:14 AM, Peter Xu <peterx@redhat.com> wrote:
> > On Mon, May 30, 2016 at 07:56:16AM +0200, Jan Kiszka wrote:
> >> On 2016-05-30 07:45, Peter Xu wrote:
[...]
> >> >
> >> > I assume you mean when host cpu is big endian. x86 was little endian,
> >> > and I was testing on x86.
> >> >
> >> > I think you are right. I should do conditional byte swap for all
> >> > uint{16/32/64} cases within the fields. For example, index_l field in
> >> > above VTD_IR_MSIAddress. And there are several other cases that need
> >> > special treatment in the patchset. Will go over and fix corresponding
> >> > issues in next version.
> >>
> >> You actually need bit-swap with bit fields, see e.g. hw/net/vmxnet3.h.
> >
> > Not noticed about bit-field ordering before... So maybe I need both?
>
> Yes, I think we will need both though, I think, byte swapping the
> whole struct will break the code but swapping individual fields is
> what we need.
>
> Myself, I'm defining bitfields as below:
>
> struct CMDCompletionWait {
>
> #ifdef __BIG_ENDIAN_BITFIELD
> uint32_t type:4; /* command type */
> uint32_t reserved:8;
> uint64_t store_addr:49; /* addr to write */
> uint32_t completion_flush:1; /* allow more executions */
> uint32_t completion_int:1; /* set MMIOWAITINT */
> uint32_t completion_store:1; /* write data to address */
I guess what we need might be this one:
uint64_t type:4; /* command type */
uint64_t reserved:8;
uint64_t store_addr:49; /* addr to write */
uint64_t completion_flush:1; /* allow more executions */
uint64_t completion_int:1; /* set MMIOWAITINT */
uint64_t completion_store:1; /* write data to address */
IIUC, if we define type:4 as uint32_t rather than uint64_t, it should
be bits [29:32] of the struct on big endian machines, not bits
[61:64].
Thanks,
-- peterx
next prev parent reply other threads:[~2016-05-30 9:17 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-17 7:15 [Qemu-devel] [PATCH v7 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 01/25] acpi: enable INTR for DMAR report structure Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 02/25] intel_iommu: allow queued invalidation for IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 03/25] intel_iommu: set IR bit for ECAP register Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 04/25] acpi: add DMAR scope definition for root IOAPIC Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 05/25] intel_iommu: define interrupt remap table addr register Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 06/25] intel_iommu: handle interrupt remap enable Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 07/25] intel_iommu: define several structs for IOMMU IR Peter Xu
2016-05-29 8:20 ` David Kiarie
2016-05-29 8:21 ` David Kiarie
2016-05-30 5:45 ` Peter Xu
2016-05-30 5:56 ` Jan Kiszka
2016-05-30 8:14 ` Peter Xu
2016-05-30 8:54 ` David Kiarie
2016-05-30 9:16 ` Peter Xu [this message]
2016-05-30 9:25 ` David Kiarie
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 08/25] x86-iommu: introduce parent class Peter Xu
2016-05-23 17:06 ` David Kiarie
2016-05-23 21:48 ` Marcel Apfelbaum
2016-05-24 10:40 ` Jan Kiszka
2016-05-24 11:02 ` David Kiarie
2016-05-24 11:29 ` David Kiarie
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 09/25] x86-iommu: provide x86_iommu_get_default Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 10/25] x86-iommu: q35: generalize find_add_as() Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 11/25] intel_iommu: add IR translation faults defines Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 12/25] intel_iommu: Add support for PCI MSI remap Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 13/25] q35: ioapic: add support for emulated IOAPIC IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 14/25] ioapic: introduce ioapic_entry_parse() helper Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 15/25] intel_iommu: add support for split irqchip Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 16/25] q35: add "intremap" parameter to enable IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 17/25] x86-iommu: introduce IEC notifiers Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 18/25] ioapic: register IOMMU IEC notifier for ioapic Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 19/25] intel_iommu: Add support for Extended Interrupt Mode Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 20/25] intel_iommu: add SID validation for IR Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 21/25] kvm-irqchip: simplify kvm_irqchip_add_msi_route Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 22/25] kvm-irqchip: i386: add hook for add/remove virq Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 23/25] kvm-irqchip: x86: add msi route notify fn Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 24/25] kvm-irqchip: do explicit commit when update irq Peter Xu
2016-05-17 7:15 ` [Qemu-devel] [PATCH v7 25/25] intel_iommu: support all masks in interrupt entry cache invalidation Peter Xu
2016-05-17 7:22 ` [Qemu-devel] [PATCH v7 00/25] IOMMU: Enable interrupt remapping for Intel IOMMU Peter Xu
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