From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53346) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7QLe-0008Ua-4a for qemu-devel@nongnu.org; Mon, 30 May 2016 12:47:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b7QLb-000596-UW for qemu-devel@nongnu.org; Mon, 30 May 2016 12:47:25 -0400 Received: from hall.aurel32.net ([2001:bc8:30d7:100::1]:59687) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b7QLb-00058N-PE for qemu-devel@nongnu.org; Mon, 30 May 2016 12:47:23 -0400 Date: Mon, 30 May 2016 18:47:01 +0200 From: Aurelien Jarno Message-ID: <20160530164701.GA27324@aurel32.net> References: <1464310815-13554-1-git-send-email-rth@twiddle.net> <1464310815-13554-7-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1464310815-13554-7-git-send-email-rth@twiddle.net> Subject: Re: [Qemu-devel] [PATCH v2 06/12] tcg/mips: Add support for fence List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, bobby.prani@gmail.com On 2016-05-26 18:00, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > tcg/mips/tcg-target.inc.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c > index 50e98ea..cad1d4d 100644 > --- a/tcg/mips/tcg-target.inc.c > +++ b/tcg/mips/tcg-target.inc.c > @@ -292,6 +292,7 @@ typedef enum { > OPC_JALR = OPC_SPECIAL | 0x09, > OPC_MOVZ = OPC_SPECIAL | 0x0A, > OPC_MOVN = OPC_SPECIAL | 0x0B, > + OPC_SYNC = OPC_SPECIAL | 0x0F, > OPC_MFHI = OPC_SPECIAL | 0x10, > OPC_MFLO = OPC_SPECIAL | 0x12, > OPC_MULT = OPC_SPECIAL | 0x18, > @@ -1636,6 +1637,9 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > const_args[4], const_args[5], true); > break; > > + case INDEX_op_fence: > + tcg_out32(s, OPC_SYNC); > + break; > case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ > case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ > case INDEX_op_call: /* Always emitted via tcg_out_call. */ > @@ -1716,6 +1720,8 @@ static const TCGTargetOpDef mips_op_defs[] = { > { INDEX_op_qemu_ld_i64, { "L", "L", "lZ", "lZ" } }, > { INDEX_op_qemu_st_i64, { "SZ", "SZ", "SZ", "SZ" } }, > #endif > + > + { INDEX_op_fence, { } }, > { -1 }, > }; Reviewed-by: Aurelien Jarno Also compiled tested, but we don't really have a way to test that so far. -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://www.aurel32.net