From: "Michael S. Tsirkin" <mst@redhat.com>
To: Dmitry Fleytman <dmitry@daynix.com>
Cc: Leonid Bloch <leonid.bloch@ravellosystems.com>,
QEMU Developers <qemu-devel@nongnu.org>,
Jason Wang <jasowang@redhat.com>,
Leonid Bloch <leonid@daynix.com>,
Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
Subject: Re: [Qemu-devel] [PATCH v6 01/17] pci: fix unaligned access in pci_xxx_quad()
Date: Mon, 30 May 2016 18:26:09 +0300 [thread overview]
Message-ID: <20160530182501-mutt-send-email-mst@redhat.com> (raw)
In-Reply-To: <A0CAFCD2-752B-4607-85CC-ED9961719392@daynix.com>
On Mon, May 30, 2016 at 06:22:35PM +0300, Dmitry Fleytman wrote:
>
> > On 30 May 2016, at 18:19 PM, Michael S. Tsirkin <mst@redhat.com> wrote:
> >
> > On Mon, May 30, 2016 at 06:14:56PM +0300, Dmitry Fleytman wrote:
> >> Does DSN generation function pass unaligned offsets?
> >> It does not look like it does…
> >>
> >>
> >> It does according to clang sanitiser.
> >
> >
> > Oh so it's a clang false positive?
>
> I think not.
> The capability itself is 8-bytes aligned but 64-bit serial number inside of it is not because of 32 bit header in front of it.
Oh right. Things like this should really go into commit log
in the future.
For now a code comment in pci set/get that explains that
alignment in capabilities is generally at dword not qword
boundary would be enough.
> >
> > --
> > MST
next prev parent reply other threads:[~2016-05-30 15:26 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-05-30 9:14 [Qemu-devel] [PATCH v6 00/17] Introduce Intel 82574 GbE Controller Emulation (e1000e) Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 01/17] pci: fix unaligned access in pci_xxx_quad() Leonid Bloch
2016-05-30 14:47 ` Michael S. Tsirkin
2016-05-30 15:05 ` Dmitry Fleytman
2016-05-30 15:11 ` Michael S. Tsirkin
2016-05-30 15:14 ` Dmitry Fleytman
2016-05-30 15:19 ` Michael S. Tsirkin
2016-05-30 15:22 ` Dmitry Fleytman
2016-05-30 15:26 ` Michael S. Tsirkin [this message]
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 02/17] msix: make msix_clr_pending() visible for clients Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 03/17] pci: Introduce define for PM capability version 1.1 Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 04/17] pcie: Add support for PCIe CAP v1 Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 05/17] pcie: Introduce function for DSN capability creation Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 06/17] vmxnet3: Use generic function for DSN capability definition Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 07/17] net: Introduce Toeplitz hash calculator Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 08/17] net: Add macros for MAC address tracing Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 09/17] vmxnet3: Use common MAC address tracing macros Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 10/17] net_pkt: Name vmxnet3 packet abstractions more generic Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 11/17] rtl8139: Move more TCP definitions to common header Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 12/17] net_pkt: Extend packet abstraction as required by e1000e functionality Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 13/17] vmxnet3: Use pci_dma_* API instead of cpu_physical_memory_* Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 14/17] e1000_regs: Add definitions for Intel 82574-specific bits Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 15/17] e1000: Move out code that will be reused in e1000e Leonid Bloch
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 16/17] net: Introduce e1000e device emulation Leonid Bloch
2016-05-30 15:10 ` Michael S. Tsirkin
2016-05-31 6:08 ` Dmitry Fleytman
2016-05-31 7:10 ` Dmitry Fleytman
2016-05-30 9:14 ` [Qemu-devel] [PATCH v6 17/17] e1000e: Introduce qtest for e1000e device Leonid Bloch
2016-05-30 14:50 ` [Qemu-devel] [PATCH v6 00/17] Introduce Intel 82574 GbE Controller Emulation (e1000e) Michael S. Tsirkin
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