From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42611) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8iJP-0003rm-Ja for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8iJJ-0003tG-4T for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:26 -0400 Received: from mga14.intel.com ([192.55.52.115]:18889) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8iJI-0003se-VG for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:21 -0400 From: Haozhong Zhang Date: Fri, 3 Jun 2016 14:09:42 +0800 Message-Id: <20160603060944.17373-1-haozhong.zhang@intel.com> Subject: [Qemu-devel] [PATCH v3 0/2] Add QEMU support for Intel local MCE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcelo Tosatti , "Michael S . Tsirkin" , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , Ashok Raj , Haozhong Zhang This is v3 of LMCE patch series. Previous ones can be found at v2: https://lists.nongnu.org/archive/html/qemu-devel/2015-12/msg01731.html v1: https://lists.nongnu.org/archive/html/qemu-devel/2015-12/msg01651.html v0: https://lists.nongnu.org/archive/html/qemu-devel/2015-12/msg01498.html Changes in v3: * LMCE can be enabled only for non-intel guests. * LMCE is disabled by default and a cpu option 'lmce=on/off' is added to explicitly enable/disable LMCE. * LMCE is disabled if KVM does not support (even though 'lmce=on'). * VM on LMCE-enabled QEMU can be only migrated to LMCE-enabled QEMU. * MCG_LMCE_P is not included in MCE_CAP_DEF and instead added to env->mcg_cap if LMCE is enabled. * Code style fix. This QEMU patch series along with the corresponding KVM patch (sent via another email with title "[PATCH v1] Add KVM support for Intel local MCE") enables Intel local MCE feature for guest. Intel Local MCE (LMCE) is a feature on Intel Skylake Server CPU that can deliver MCE to a single processor thread instead of broadcasting to all threads, which can reduce software's load when processing MCE on machines with a large number of processor threads. The technical details of LMCE can be found in Intel SDM Vol 3, Chapter "Machine-Check Architecture" (search for 'LMCE'). Basically, * The capability of LMCE is indicated by bit 27 (MCG_LMCE_P) of MSR_IA32_MCG_CAP. * LMCE is enabled by setting bit 20 (MSR_IA32_FEATURE_CONTROL_LMCE) of MSR_IA32_FEATURE_CONTROL and bit 0 (MCG_EXT_CTL_LMCE_EN) of MSR_IA32_MCG_EXT_CTL. * Software can determine if a MCE is local to the current processor thread by checking bit 2 (MCG_STATUS_LMCE) of MSR_IA32_MCG_STATUS. Haozhong Zhang (2): target-i386: KVM: add basic Intel LMCE support target-i386: add migration support for Intel LMCE include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 27 +++++++++++++++++++++++++++ target-i386/cpu.h | 18 +++++++++++++++++- target-i386/kvm.c | 35 +++++++++++++++++++++++++++++++---- target-i386/machine.c | 24 ++++++++++++++++++++++++ 5 files changed, 105 insertions(+), 6 deletions(-) -- 2.8.3