From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42642) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8iJd-00041c-8d for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1b8iJY-0003u2-V2 for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:40 -0400 Received: from mga14.intel.com ([192.55.52.115]:53164) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1b8iJY-0003tw-H9 for qemu-devel@nongnu.org; Fri, 03 Jun 2016 02:10:36 -0400 From: Haozhong Zhang Date: Fri, 3 Jun 2016 14:09:44 +0800 Message-Id: <20160603060944.17373-3-haozhong.zhang@intel.com> In-Reply-To: <20160603060944.17373-1-haozhong.zhang@intel.com> References: <20160603060944.17373-1-haozhong.zhang@intel.com> Subject: [Qemu-devel] [PATCH v3 2/2] target-i386: add migration support for Intel LMCE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , Marcelo Tosatti , "Michael S . Tsirkin" , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , Ashok Raj , Haozhong Zhang LMCE is disabled by default, but a cpu option 'lmce=on/off' is provided to enable/disable it. Migration is only allowed between VCPUs with the same lmce option. Signed-off-by: Haozhong Zhang --- Cc: "Michael S. Tsirkin" Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Cc: Boris Petkov Cc: Tony Luck Cc: Andi Kleen Cc: Ashok Raj --- include/hw/i386/pc.h | 7 ++++++- target-i386/cpu.c | 1 + target-i386/cpu.h | 5 +++++ target-i386/machine.c | 24 ++++++++++++++++++++++++ 4 files changed, 36 insertions(+), 1 deletion(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index ca23609..058eef9 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -357,7 +357,12 @@ int e820_get_num_entries(void); bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); #define PC_COMPAT_2_6 \ - HW_COMPAT_2_6 + HW_COMPAT_2_6 \ + {\ + .driver = TYPE_X86_CPU,\ + .property = "lmce",\ + .value = "off",\ + }, #define PC_COMPAT_2_5 \ PC_COMPAT_2_6 \ diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 9b4dbab..c69cc17 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -3232,6 +3232,7 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), DEFINE_PROP_UINT32("xlevel2", X86CPU, env.cpuid_xlevel2, 0), DEFINE_PROP_STRING("hv-vendor-id", X86CPU, hyperv_vendor_id), + DEFINE_PROP_BOOL("lmce", X86CPU, enable_lmce, false), DEFINE_PROP_END_OF_LIST() }; diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2d411ba..b512fd6 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1182,6 +1182,11 @@ struct X86CPU { */ bool enable_pmu; + /* Enable LMCE support which is set via cpu option 'lmce=on/off'. LMCE is + * disabled by default to avoid breaking the migration between QEMU with + * different LMCE support. Only migrating between QEMU with the same LMCE + * support is allowed. + */ bool enable_lmce; /* in order to simplify APIC support, we leave this pointer to the diff --git a/target-i386/machine.c b/target-i386/machine.c index cb9adf2..b55d376 100644 --- a/target-i386/machine.c +++ b/target-i386/machine.c @@ -347,6 +347,11 @@ static int cpu_post_load(void *opaque, int version_id) return -EINVAL; } + if (!cpu->enable_lmce && (env->mcg_cap & MCG_LMCE_P)) { + error_report("LMCE not enabled"); + return -EINVAL; + } + /* * Real mode guest segments register DPL should be zero. * Older KVM version were setting it wrongly. @@ -896,6 +901,24 @@ static const VMStateDescription vmstate_tsc_khz = { } }; +static bool mcg_ext_ctl_needed(void *opaque) +{ + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; + return cpu->enable_lmce && env->mcg_ext_ctl; +} + +static const VMStateDescription vmstate_mcg_ext_ctl = { + .name = "cpu/mcg_ext_ctl", + .version_id = 1, + .minimum_version_id = 1, + .needed = mcg_ext_ctl_needed, + .fields = (VMStateField[]) { + VMSTATE_UINT64(env.mcg_ext_ctl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, @@ -1022,6 +1045,7 @@ VMStateDescription vmstate_x86_cpu = { #ifdef TARGET_X86_64 &vmstate_pkru, #endif + &vmstate_mcg_ext_ctl, NULL } }; -- 2.8.3