From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from eggs.gnu.org ([2001:4830:134:3::10]:43130)
	by lists.gnu.org with esmtp (Exim 4.71)
	(envelope-from <thement@ibawizard.net>) id 1b8rIO-00069L-1t
	for qemu-devel@nongnu.org; Fri, 03 Jun 2016 11:46:00 -0400
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <thement@ibawizard.net>) id 1b8rIJ-0007T9-Rw
	for qemu-devel@nongnu.org; Fri, 03 Jun 2016 11:45:59 -0400
Received: from ibawizard.net ([82.208.49.253]:60568 helo=mengele.ibawizard.net)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <thement@ibawizard.net>) id 1b8rIJ-0007T5-LB
	for qemu-devel@nongnu.org; Fri, 03 Jun 2016 11:45:55 -0400
Date: Fri, 3 Jun 2016 17:45:49 +0200
From: Jakub Horak <thement@ibawizard.net>
Message-ID: <20160603154549.GA31406@ibawizard>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
Subject: [Qemu-devel] Bug in ppc/BookE wait instruction
List-Id: <qemu-devel.nongnu.org>
List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel/>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: qemu-devel@nongnu.org

Hello,
I think there's a bug in "wait" instruction code generator for PowerPC
architecture. It doesn't make sense to store a non-initialized register.

Best regards,
Jakub Horak


diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index f5ceae5..6af567b 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -3439,7 +3439,7 @@ static void gen_sync(DisasContext *ctx)
 /* wait */
 static void gen_wait(DisasContext *ctx)
 {
-    TCGv_i32 t0 = tcg_temp_new_i32();
+    TCGv_i32 t0 = tcg_const_i32(1);
     tcg_gen_st_i32(t0, cpu_env,
                    -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
     tcg_temp_free_i32(t0);