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Date: Mon, 6 Jun 2016 17:32:38 +0100
From: Mark Rutland <mark.rutland@arm.com>
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Subject: Re: [Qemu-devel] [kvm-unit-tests PATCH v2 03/10] arm/arm64: smp:
 support more than 8 cpus
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To: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
Cc: Andrew Jones <drjones@redhat.com>, kvm@vger.kernel.org, marc.zyngier@arm.com, andre.przywara@arm.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org, pbonzini@redhat.com, kvmarm@lists.cs.columbia.edu

On Mon, Jun 06, 2016 at 05:22:49PM +0100, Alex Benn=C3=A9e wrote:
> Andrew Jones <drjones@redhat.com> writes:
> > +#define MPIDR_LEVEL_SHIFT(level) \
> > +	(((1 << level) >> 1) << 3)
> > +#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
> > +	((mpidr >> MPIDR_LEVEL_SHIFT(level)) & 0xff)
>=20
> Doesn't Aff3 break this little macro? It sits at 32:39 with a gap for
> MT, RES0, U, RES1 for bits 25:31

It works, it's just a little bit magic:

(gdb) p (((1 << 0) >> 1) << 3)
$1 =3D 0
(gdb) p (((1 << 1) >> 1) << 3)
$2 =3D 8
(gdb) p (((1 << 2) >> 1) << 3)
$3 =3D 16
(gdb) p (((1 << 3) >> 1) << 3)
$4 =3D 32
(gdb)=20

We do the same in arch/arm64/include/asm/cputype.h since b058450f38c337d1
("arm64: kernel: add MPIDR_EL1 accessors macros").

Thanks,
Mark.