From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36215) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bD16d-00053q-4S for qemu-devel@nongnu.org; Tue, 14 Jun 2016 23:03:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bD16X-0003IE-Hj for qemu-devel@nongnu.org; Tue, 14 Jun 2016 23:03:02 -0400 Date: Wed, 15 Jun 2016 11:09:48 +1000 From: David Gibson Message-ID: <20160615010948.GZ4882@voom.fritz.box> References: <1465795496-15071-1-git-send-email-clg@kaod.org> <1465795496-15071-6-git-send-email-clg@kaod.org> <20160614063405.GQ4882@voom.fritz.box> <575FA752.3070208@kaod.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="qicHaSekiYEWE95x" Content-Disposition: inline In-Reply-To: <575FA752.3070208@kaod.org> Subject: Re: [Qemu-devel] [PATCH 05/10] ppc: Fix generation if ISI/DSI vs. HV mode List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-1?Q?C=E9dric?= Le Goater Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Benjamin Herrenschmidt , Andrei Warkentin --qicHaSekiYEWE95x Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Tue, Jun 14, 2016 at 08:42:26AM +0200, C=E9dric Le Goater wrote: > On 06/14/2016 08:34 AM, David Gibson wrote: > > On Mon, Jun 13, 2016 at 07:24:51AM +0200, C=E9dric Le Goater wrote: > >> From: Benjamin Herrenschmidt > >> > >> Under some circumstances, we need to direct ISI and DSI interrupts > >> at the hypervisor, turning them into HISI/HDSI, and using different > >> SPRs (HDSISR and HDAR) depending on the combination of MSR_DR and > >> the corresponding VPM bits in LPCR. > >> > >> This moves part of the code into helpers that are fixed to select > >> the right exception type and registers. On pre-P7 processors, LPCR > >> is 0 which provides the old behaviour of directing the interrupts > >> at the supervisor. > >> > >> Thanks to Andrei Warkentin for finding a bug when HV=3D1 > >> > >> Signed-off-by: Benjamin Herrenschmidt > >> Reviewed-by: David Gibson > >> --- > >> target-ppc/mmu-hash64.c | 69 +++++++++++++++++++++++++++++++++++-----= --------- > >> 1 file changed, 50 insertions(+), 19 deletions(-) > >> > >> diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c > >> index 668da5e22653..072a952c8bd5 100644 > >> --- a/target-ppc/mmu-hash64.c > >> +++ b/target-ppc/mmu-hash64.c > >> @@ -613,6 +613,47 @@ unsigned ppc_hash64_hpte_page_shift_noslb(PowerPC= CPU *cpu, > >> return 0; > >> } > >> =20 > >> +static void ppc_hash64_set_isi(CPUState *cs, CPUPPCState *env, > >> + uint64_t error_code) > >> +{ > >> + bool vpm; > >> + > >> + if (msr_ir) { > >> + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > >> + } else { > >> + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > >> + } > >> + if (vpm && !msr_hv) { > >> + cs->exception_index =3D POWERPC_EXCP_HISI; > >=20 > > In the ISI case, you use HISI if !msr_hv.. > >=20 > >> + } else { > >> + cs->exception_index =3D POWERPC_EXCP_ISI; > >> + } > >> + env->error_code =3D error_code; > >> +} > >> + > >> +static void ppc_hash64_set_dsi(CPUState *cs, CPUPPCState *env, uint64= _t dar, > >> + uint64_t dsisr) > >> +{ > >> + bool vpm; > >> + > >> + if (msr_dr) { > >> + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM1); > >> + } else { > >> + vpm =3D !!(env->spr[SPR_LPCR] & LPCR_VPM0); > >> + } > >> + if (vpm && msr_hv) { > >> + cs->exception_index =3D POWERPC_EXCP_HDSI; > >=20 > > ..but in the DSI case you use HDSI if msr_hv. Is that really right? >=20 > No. I forgot to add this patch from Andrei : >=20 > https://github.com/legoater/qemu/commit/e218fd3ba945bb0f483f5f12bedbb74d= 897cd5b9 >=20 > I will send it as a fix. Given that there are a number of tweaks this series needs, I'd prefer to see it folded in rather than as a separate patch. >=20 > C. =20 >=20 > >> + env->spr[SPR_HDAR] =3D dar; > >> + env->spr[SPR_HDSISR] =3D dsisr; > >> + } else { > >> + cs->exception_index =3D POWERPC_EXCP_DSI; > >> + env->spr[SPR_DAR] =3D dar; > >> + env->spr[SPR_DSISR] =3D dsisr; > >> + } > >> + env->error_code =3D 0; > >> +} > >> + > >> + > >> int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, > >> int rwx, int mmu_idx) > >> { > >> @@ -623,7 +664,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, v= addr eaddr, > >> hwaddr pte_offset; > >> ppc_hash_pte64_t pte; > >> int pp_prot, amr_prot, prot; > >> - uint64_t new_pte1; > >> + uint64_t new_pte1, dsisr; > >> const int need_prot[] =3D {PAGE_READ, PAGE_WRITE, PAGE_EXEC}; > >> hwaddr raddr; > >> =20 > >> @@ -657,26 +698,21 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu,= vaddr eaddr, > >> =20 > >> /* 3. Check for segment level no-execute violation */ > >> if ((rwx =3D=3D 2) && (slb->vsid & SLB_VSID_N)) { > >> - cs->exception_index =3D POWERPC_EXCP_ISI; > >> - env->error_code =3D 0x10000000; > >> + ppc_hash64_set_isi(cs, env, 0x10000000); > >> return 1; > >> } > >> =20 > >> /* 4. Locate the PTE in the hash table */ > >> pte_offset =3D ppc_hash64_htab_lookup(cpu, slb, eaddr, &pte); > >> if (pte_offset =3D=3D -1) { > >> + dsisr =3D 0x40000000; > >> if (rwx =3D=3D 2) { > >> - cs->exception_index =3D POWERPC_EXCP_ISI; > >> - env->error_code =3D 0x40000000; > >> + ppc_hash64_set_isi(cs, env, dsisr); > >> } else { > >> - cs->exception_index =3D POWERPC_EXCP_DSI; > >> - env->error_code =3D 0; > >> - env->spr[SPR_DAR] =3D eaddr; > >> if (rwx =3D=3D 1) { > >> - env->spr[SPR_DSISR] =3D 0x42000000; > >> - } else { > >> - env->spr[SPR_DSISR] =3D 0x40000000; > >> + dsisr |=3D 0x02000000; > >> } > >> + ppc_hash64_set_dsi(cs, env, eaddr, dsisr); > >> } > >> return 1; > >> } > >> @@ -705,14 +741,9 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, = vaddr eaddr, > >> /* Access right violation */ > >> qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n"); > >> if (rwx =3D=3D 2) { > >> - cs->exception_index =3D POWERPC_EXCP_ISI; > >> - env->error_code =3D 0x08000000; > >> + ppc_hash64_set_isi(cs, env, 0x08000000); > >> } else { > >> - target_ulong dsisr =3D 0; > >> - > >> - cs->exception_index =3D POWERPC_EXCP_DSI; > >> - env->error_code =3D 0; > >> - env->spr[SPR_DAR] =3D eaddr; > >> + dsisr =3D 0; > >> if (need_prot[rwx] & ~pp_prot) { > >> dsisr |=3D 0x08000000; > >> } > >> @@ -722,7 +753,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, v= addr eaddr, > >> if (need_prot[rwx] & ~amr_prot) { > >> dsisr |=3D 0x00200000; > >> } > >> - env->spr[SPR_DSISR] =3D dsisr; > >> + ppc_hash64_set_dsi(cs, env, eaddr, dsisr); > >> } > >> return 1; > >> } > >=20 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --qicHaSekiYEWE95x Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXYKrcAAoJEGw4ysog2bOS2dAP/R/gWfnnvIuYyFZdPUWxz+/C +S8p2VGTic8ibzio5gWpp1TnYmf1hn+PsyQ7JreDbdq1Xi2KaPkLF2aar17XKyFL 2O3KaAS4vlZv1hhfvck2Px7PrBgfX/v0LBGC8MbnrMYkeiG4bLLOJYErFrgMkzG8 ZSpwT9+TSSCsjwWQvnYkMth5ehjfxmSjLEGKkiWLiMBjiGh4oB88riMw6Bkg5aQf +utABD7JvwJHnpNoJvk1DnFmXdLEhekLAwb4ORTRAbJD/JTlmGjQVfAD1yUSeMQs J14IDutxhC0yanc2YyBqW9yhkGnCmwoSf/lzbgjt14V238G7oBPofRxzqMnmP2W2 USKQ7K2vLWXPyBq4kCpDAAXTXO3MuNO8w7jTwoeJTAmi5jtJQQ1Fic3x3A7BkzEi csERvCjAkcoVgtlI07BGQBF2nZzlPL6yAxib0Sz1EBwzyR/1ZrZDObZnLZVOKUki CjPYr4l6rsUKTxs7MQHrRmLxtzvtJx9i1o6RbB2KQI7tlr2/iXgUFFZ+/wDryGAG HlBohfCIYa5vmqema9J3gsNfpZARY+3NEjIWo+MhJvTCMPG5Agg7Ew+Y9baARZzr x8cqCQzUFDhUdRjAVogITjWuQOuXLJKDi0RDfamH1idFKJK5h6r8Am6hTNzQZBLc dOmZUCWxVBnb3mdyrbD/ =+bFs -----END PGP SIGNATURE----- --qicHaSekiYEWE95x--