From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47670) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDQRp-00077c-7P for qemu-devel@nongnu.org; Thu, 16 Jun 2016 02:06:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bDQRm-0001Uq-0l for qemu-devel@nongnu.org; Thu, 16 Jun 2016 02:06:37 -0400 Received: from mga02.intel.com ([134.134.136.20]:34783) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bDQRl-0001U7-Qj for qemu-devel@nongnu.org; Thu, 16 Jun 2016 02:06:33 -0400 From: Haozhong Zhang Date: Thu, 16 Jun 2016 14:06:18 +0800 Message-Id: <20160616060621.30422-1-haozhong.zhang@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PATCH v4 0/3] Add QEMU support for Intel local MCE List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj , Haozhong Zhang Changes in v4: * Abort starting QEMU if lmce option is present but host does support LMCE. (Eduardo Habkost) * Remove setting MSR_IA32_FEATURE_CONTROL, which should be left to guest. (Radim Krčmá, Paolo Bonzini * Adjust error messages in mce_init(). (Boris Petkov) * Move adding option 'lmce' to patch 1. (Eduardo Habkost, Paolo Bonzini) * Adjust LMCE error message in cpu_post_load(). (Eduardo Habkost) * (Patch 3) Add a fw_cfg file 'etc/msr_feature_control' to advise bits should be set in MSR_IA32_FEATURE_CONTROL. (Paolo Bonzini) * Fix SOB chain in patch 1. Changes in v3: * LMCE can be enabled only for non-intel guests. * LMCE is disabled by default and a cpu option 'lmce=on/off' is added to explicitly enable/disable LMCE. * LMCE is disabled if KVM does not support (even though 'lmce=on'). * VM on LMCE-enabled QEMU can be only migrated to LMCE-enabled QEMU. * MCG_LMCE_P is not included in MCE_CAP_DEF and instead added to env->mcg_cap if LMCE is enabled. * Code style fix. This QEMU patch series along with the corresponding KVM patch series (sent via another email with title "[PATCH v2 0/3] Add KVM support for Intel local MCE") enables Intel local MCE feature for guest. Intel Local MCE (LMCE) is a feature on Intel Skylake Server CPU that can deliver MCE to a single processor thread instead of broadcasting to all threads, which can reduce software's load when processing MCE on machines with a large number of processor threads. The technical details of LMCE can be found in Intel SDM Vol 3, Chapter "Machine-Check Architecture" (search for 'LMCE'). Basically, * The capability of LMCE is indicated by bit 27 (MCG_LMCE_P) of MSR_IA32_MCG_CAP. * LMCE is enabled by setting bit 20 (MSR_IA32_FEATURE_CONTROL_LMCE) of MSR_IA32_FEATURE_CONTROL and bit 0 (MCG_EXT_CTL_LMCE_EN) of MSR_IA32_MCG_EXT_CTL. * Software can determine if a MCE is local to the current processor thread by checking bit 2 (MCG_STATUS_LMCE) of MSR_IA32_MCG_STATUS. Ashok Raj (1): target-i386: KVM: add basic Intel LMCE support Haozhong Zhang (2): target-i386: add migration support for Intel LMCE i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg hw/i386/pc.c | 28 ++++++++++++++++++++++++++++ target-i386/cpu.c | 23 +++++++++++++++++++++++ target-i386/cpu.h | 16 ++++++++++++++++ target-i386/kvm.c | 35 +++++++++++++++++++++++++++++++---- target-i386/machine.c | 25 +++++++++++++++++++++++++ 5 files changed, 123 insertions(+), 4 deletions(-) -- 2.9.0