From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46511) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7W7-00041k-Tm for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:05:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bE7W3-0005Pp-M7 for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:05:54 -0400 From: Pranith Kumar Date: Sat, 18 Jun 2016 00:03:42 -0400 Message-Id: <20160618040343.19517-14-bobby.prani@gmail.com> In-Reply-To: <20160618040343.19517-1-bobby.prani@gmail.com> References: <20160618040343.19517-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [RFC v3 PATCH 13/14] aarch64: Generate fences for aarch64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell , "open list:ARM" , "open list:All patches CC here" Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, rth@twiddle.net Signed-off-by: Pranith Kumar --- target-arm/translate-a64.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index ce8141a..fa24bf2 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -1250,7 +1250,7 @@ static void handle_sync(DisasContext *s, uint32_t insn, return; case 4: /* DSB */ case 5: /* DMB */ - /* We don't emulate caches so barriers are no-ops */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); return; case 6: /* ISB */ /* We need to break the TB after this insn to execute @@ -1855,23 +1855,31 @@ static void disas_ldst_excl(DisasContext *s, uint32_t insn) } tcg_addr = read_cpu_reg_sp(s, rn, 1); - /* Note that since TCG is single threaded load-acquire/store-release - * semantics require no extra if (is_lasr) { ... } handling. - */ - if (is_excl) { if (!is_store) { s->is_ldex = true; gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); + if (is_lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ); + } } else { + if (is_lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL); + } gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); } } else { TCGv_i64 tcg_rt = cpu_reg(s, rt); if (is_store) { + if (is_lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_REL); + } do_gpr_st(s, tcg_rt, tcg_addr, size); } else { do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false); + if (is_lasr) { + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_ACQ); + } } } } -- 2.9.0