From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46881) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7YZ-0007G5-Eb for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:08:28 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bE7YW-0005p6-58 for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:08:27 -0400 Received: from mail-yw0-x244.google.com ([2607:f8b0:4002:c05::244]:35383) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bE7YW-0005oh-0p for qemu-devel@nongnu.org; Sat, 18 Jun 2016 00:08:24 -0400 Received: by mail-yw0-x244.google.com with SMTP id z186so280640ywd.2 for ; Fri, 17 Jun 2016 21:08:24 -0700 (PDT) From: Pranith Kumar Date: Sat, 18 Jun 2016 00:08:20 -0400 Message-Id: <20160618040820.23275-1-bobby.prani@gmail.com> In-Reply-To: <20160618040343.19517-1-bobby.prani@gmail.com> References: <20160618040343.19517-1-bobby.prani@gmail.com> Subject: [Qemu-devel] [RFC v3 PATCH 00/14] tcg: Add fence gen support List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alex.bennee@linaro.org, serge.fdrv@gmail.com, rth@twiddle.net, qemu-devel@nongnu.org Hello, The following series adds fence instruction generation support to TCG. Based on feedback to the last series, I added the four combinations of orderings modeled after Sparc membar. This has been tested and confirmed to fix ordering issues on x86/armv7/aarch64 hosts with MTTCG enabled for an ARMv7 guest using KVM unit tests. TODO: * The acquire/release order is not utilized yet. Currently we generate SC barriers even for acquire/release barriers. The idea is to write a pass which combines acquire/release barrier with its corresponding load/store operation to generate the load acquire/store release instruction on hosts which have such instruction(aarch64 for now). Also the pass should try to optimize some trivial scenarios like removing unnecessary barrier instructions. * Complete support for fence generation in other architectures. v3: - Create different types of barriers. The barrier tcg opcode now takes an argument to generate the appropriate barrier instruction. - Also add acquire/release/sc ordering flag to argument. v2: - Rebase on Richard's patches generating fences for other architectures. v1: - Initial version: Introduce memory barrier tcg opcode. Pranith Kumar (14): Introduce TCGOpcode for memory barrier tcg/i386: Add support for fence tcg/aarch64: Add support for fence tcg/arm: Add support for fence tcg/ia64: Add support for fence tcg/mips: Add support for fence tcg/ppc: Add support for fence tcg/s390: Add support for fence tcg/sparc: Add support for fence tcg/tci: Add support for fence target-arm: Generate fences in ARMv7 frontend target-alpha: Generate fence op aarch64: Generate fences for aarch64 target-i386: Generate fences for x86 target-alpha/translate.c | 4 ++-- target-arm/translate-a64.c | 18 ++++++++++++----- target-arm/translate.c | 4 ++-- target-i386/translate.c | 4 ++++ tcg/README | 17 ++++++++++++++++ tcg/aarch64/tcg-target.inc.c | 25 +++++++++++++++++++++++ tcg/arm/tcg-target.inc.c | 18 +++++++++++++++++ tcg/i386/tcg-target.inc.c | 47 ++++++++++++++++++++++++++++++++++++++++++++ tcg/ia64/tcg-target.inc.c | 5 +++++ tcg/mips/tcg-target.inc.c | 6 ++++++ tcg/ppc/tcg-target.inc.c | 24 ++++++++++++++++++++++ tcg/s390/tcg-target.inc.c | 9 +++++++++ tcg/sparc/tcg-target.inc.c | 25 +++++++++++++++++++++++ tcg/tcg-op.c | 11 +++++++++++ tcg/tcg-op.h | 2 ++ tcg/tcg-opc.h | 2 ++ tcg/tcg.h | 14 +++++++++++++ tcg/tci/tcg-target.inc.c | 3 +++ tci.c | 3 +++ 19 files changed, 232 insertions(+), 9 deletions(-) -- 2.9.0