* [Qemu-devel] [PATCH v2] target-ppc: Fix rlwimi, rlwinm, rlwnm
@ 2016-06-18 5:19 Richard Henderson
2016-06-18 17:34 ` Anton Blanchard
0 siblings, 1 reply; 3+ messages in thread
From: Richard Henderson @ 2016-06-18 5:19 UTC (permalink / raw)
To: qemu-devel; +Cc: anton, david, qemu-ppc
In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
considering the effect of a mask value that wraps around to
the high bits of the word.
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
target-ppc/translate.c | 73 +++++++++++++++++++++++++++++++++++---------------
1 file changed, 51 insertions(+), 22 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b689475..23bc054 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -1636,7 +1636,6 @@ static void gen_rlwimi(DisasContext *ctx)
tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
} else {
target_ulong mask;
- TCGv_i32 t0;
TCGv t1;
#if defined(TARGET_PPC64)
@@ -1645,12 +1644,21 @@ static void gen_rlwimi(DisasContext *ctx)
#endif
mask = MASK(mb, me);
- t0 = tcg_temp_new_i32();
t1 = tcg_temp_new();
- tcg_gen_trunc_tl_i32(t0, t_rs);
- tcg_gen_rotli_i32(t0, t0, sh);
- tcg_gen_extu_i32_tl(t1, t0);
- tcg_temp_free_i32(t0);
+ if (mask <= 0xffffffffu) {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, t_rs);
+ tcg_gen_rotli_i32(t0, t0, sh);
+ tcg_gen_extu_i32_tl(t1, t0);
+ tcg_temp_free_i32(t0);
+ } else {
+#if defined(TARGET_PPC64)
+ tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
+ tcg_gen_rotli_i64(t1, t1, sh);
+#else
+ g_assert_not_reached();
+#endif
+ }
tcg_gen_andi_tl(t1, t1, mask);
tcg_gen_andi_tl(t_ra, t_ra, ~mask);
@@ -1678,20 +1686,28 @@ static void gen_rlwinm(DisasContext *ctx)
tcg_gen_ext32u_tl(t_ra, t_rs);
tcg_gen_shri_tl(t_ra, t_ra, mb);
} else {
+ target_ulong mask;
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
- if (sh == 0) {
- tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
- } else {
- TCGv_i32 t0 = tcg_temp_new_i32();
+ mask = MASK(mb, me);
+ if (mask <= 0xffffffffu) {
+ TCGv_i32 t0 = tcg_temp_new_i32();
tcg_gen_trunc_tl_i32(t0, t_rs);
tcg_gen_rotli_i32(t0, t0, sh);
- tcg_gen_andi_i32(t0, t0, MASK(mb, me));
+ tcg_gen_andi_i32(t0, t0, mask);
tcg_gen_extu_i32_tl(t_ra, t0);
tcg_temp_free_i32(t0);
+ } else {
+#if defined(TARGET_PPC64)
+ tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
+ tcg_gen_rotli_i64(t_ra, t_ra, sh);
+ tcg_gen_andi_i64(t_ra, t_ra, mask);
+#else
+ g_assert_not_reached();
+#endif
}
}
if (unlikely(Rc(ctx->opcode) != 0)) {
@@ -1707,24 +1723,37 @@ static void gen_rlwnm(DisasContext *ctx)
TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
uint32_t mb = MB(ctx->opcode);
uint32_t me = ME(ctx->opcode);
- TCGv_i32 t0, t1;
+ target_ulong mask;
#if defined(TARGET_PPC64)
mb += 32;
me += 32;
#endif
+ mask = MASK(mb, me);
- t0 = tcg_temp_new_i32();
- t1 = tcg_temp_new_i32();
- tcg_gen_trunc_tl_i32(t0, t_rb);
- tcg_gen_trunc_tl_i32(t1, t_rs);
- tcg_gen_andi_i32(t0, t0, 0x1f);
- tcg_gen_rotl_i32(t1, t1, t0);
- tcg_temp_free_i32(t0);
+ if (mask <= 0xffffffffu) {
+ TCGv_i32 t0 = tcg_temp_new_i32();
+ TCGv_i32 t1 = tcg_temp_new_i32();
+ tcg_gen_trunc_tl_i32(t0, t_rb);
+ tcg_gen_trunc_tl_i32(t1, t_rs);
+ tcg_gen_andi_i32(t0, t0, 0x1f);
+ tcg_gen_rotl_i32(t1, t1, t0);
+ tcg_gen_extu_i32_tl(t_ra, t1);
+ tcg_temp_free_i32(t0);
+ tcg_temp_free_i32(t1);
+ } else {
+#if defined(TARGET_PPC64)
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ tcg_gen_andi_i64(t0, t_rb, 0x1f);
+ tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
+ tcg_gen_rotl_i64(t_ra, t_ra, t0);
+ tcg_temp_free_i64(t0);
+#else
+ g_assert_not_reached();
+#endif
+ }
- tcg_gen_andi_i32(t1, t1, MASK(mb, me));
- tcg_gen_extu_i32_tl(t_ra, t1);
- tcg_temp_free_i32(t1);
+ tcg_gen_andi_tl(t_ra, t_ra, mask);
if (unlikely(Rc(ctx->opcode) != 0)) {
gen_set_Rc0(ctx, t_ra);
--
2.5.5
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target-ppc: Fix rlwimi, rlwinm, rlwnm
2016-06-18 5:19 [Qemu-devel] [PATCH v2] target-ppc: Fix rlwimi, rlwinm, rlwnm Richard Henderson
@ 2016-06-18 17:34 ` Anton Blanchard
2016-06-20 2:12 ` David Gibson
0 siblings, 1 reply; 3+ messages in thread
From: Anton Blanchard @ 2016-06-18 17:34 UTC (permalink / raw)
To: Richard Henderson; +Cc: qemu-devel, david, qemu-ppc
Hi rth,
> In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
> considering the effect of a mask value that wraps around to
> the high bits of the word.
Thanks, that passes my tests.
Tested-by: Anton Blanchard <anton@samba.org>
Anton
> Signed-off-by: Richard Henderson <rth@twiddle.net>
> ---
> target-ppc/translate.c | 73
> +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 51
> insertions(+), 22 deletions(-)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index b689475..23bc054 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -1636,7 +1636,6 @@ static void gen_rlwimi(DisasContext *ctx)
> tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
> } else {
> target_ulong mask;
> - TCGv_i32 t0;
> TCGv t1;
>
> #if defined(TARGET_PPC64)
> @@ -1645,12 +1644,21 @@ static void gen_rlwimi(DisasContext *ctx)
> #endif
> mask = MASK(mb, me);
>
> - t0 = tcg_temp_new_i32();
> t1 = tcg_temp_new();
> - tcg_gen_trunc_tl_i32(t0, t_rs);
> - tcg_gen_rotli_i32(t0, t0, sh);
> - tcg_gen_extu_i32_tl(t1, t0);
> - tcg_temp_free_i32(t0);
> + if (mask <= 0xffffffffu) {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + tcg_gen_trunc_tl_i32(t0, t_rs);
> + tcg_gen_rotli_i32(t0, t0, sh);
> + tcg_gen_extu_i32_tl(t1, t0);
> + tcg_temp_free_i32(t0);
> + } else {
> +#if defined(TARGET_PPC64)
> + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
> + tcg_gen_rotli_i64(t1, t1, sh);
> +#else
> + g_assert_not_reached();
> +#endif
> + }
>
> tcg_gen_andi_tl(t1, t1, mask);
> tcg_gen_andi_tl(t_ra, t_ra, ~mask);
> @@ -1678,20 +1686,28 @@ static void gen_rlwinm(DisasContext *ctx)
> tcg_gen_ext32u_tl(t_ra, t_rs);
> tcg_gen_shri_tl(t_ra, t_ra, mb);
> } else {
> + target_ulong mask;
> #if defined(TARGET_PPC64)
> mb += 32;
> me += 32;
> #endif
> - if (sh == 0) {
> - tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
> - } else {
> - TCGv_i32 t0 = tcg_temp_new_i32();
> + mask = MASK(mb, me);
>
> + if (mask <= 0xffffffffu) {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> tcg_gen_trunc_tl_i32(t0, t_rs);
> tcg_gen_rotli_i32(t0, t0, sh);
> - tcg_gen_andi_i32(t0, t0, MASK(mb, me));
> + tcg_gen_andi_i32(t0, t0, mask);
> tcg_gen_extu_i32_tl(t_ra, t0);
> tcg_temp_free_i32(t0);
> + } else {
> +#if defined(TARGET_PPC64)
> + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
> + tcg_gen_rotli_i64(t_ra, t_ra, sh);
> + tcg_gen_andi_i64(t_ra, t_ra, mask);
> +#else
> + g_assert_not_reached();
> +#endif
> }
> }
> if (unlikely(Rc(ctx->opcode) != 0)) {
> @@ -1707,24 +1723,37 @@ static void gen_rlwnm(DisasContext *ctx)
> TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
> uint32_t mb = MB(ctx->opcode);
> uint32_t me = ME(ctx->opcode);
> - TCGv_i32 t0, t1;
> + target_ulong mask;
>
> #if defined(TARGET_PPC64)
> mb += 32;
> me += 32;
> #endif
> + mask = MASK(mb, me);
>
> - t0 = tcg_temp_new_i32();
> - t1 = tcg_temp_new_i32();
> - tcg_gen_trunc_tl_i32(t0, t_rb);
> - tcg_gen_trunc_tl_i32(t1, t_rs);
> - tcg_gen_andi_i32(t0, t0, 0x1f);
> - tcg_gen_rotl_i32(t1, t1, t0);
> - tcg_temp_free_i32(t0);
> + if (mask <= 0xffffffffu) {
> + TCGv_i32 t0 = tcg_temp_new_i32();
> + TCGv_i32 t1 = tcg_temp_new_i32();
> + tcg_gen_trunc_tl_i32(t0, t_rb);
> + tcg_gen_trunc_tl_i32(t1, t_rs);
> + tcg_gen_andi_i32(t0, t0, 0x1f);
> + tcg_gen_rotl_i32(t1, t1, t0);
> + tcg_gen_extu_i32_tl(t_ra, t1);
> + tcg_temp_free_i32(t0);
> + tcg_temp_free_i32(t1);
> + } else {
> +#if defined(TARGET_PPC64)
> + TCGv_i64 t0 = tcg_temp_new_i64();
> + tcg_gen_andi_i64(t0, t_rb, 0x1f);
> + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
> + tcg_gen_rotl_i64(t_ra, t_ra, t0);
> + tcg_temp_free_i64(t0);
> +#else
> + g_assert_not_reached();
> +#endif
> + }
>
> - tcg_gen_andi_i32(t1, t1, MASK(mb, me));
> - tcg_gen_extu_i32_tl(t_ra, t1);
> - tcg_temp_free_i32(t1);
> + tcg_gen_andi_tl(t_ra, t_ra, mask);
>
> if (unlikely(Rc(ctx->opcode) != 0)) {
> gen_set_Rc0(ctx, t_ra);
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target-ppc: Fix rlwimi, rlwinm, rlwnm
2016-06-18 17:34 ` Anton Blanchard
@ 2016-06-20 2:12 ` David Gibson
0 siblings, 0 replies; 3+ messages in thread
From: David Gibson @ 2016-06-20 2:12 UTC (permalink / raw)
To: Anton Blanchard; +Cc: Richard Henderson, qemu-devel, qemu-ppc
[-- Attachment #1: Type: text/plain, Size: 5382 bytes --]
On Sun, Jun 19, 2016 at 03:34:35AM +1000, Anton Blanchard wrote:
> Hi rth,
>
> > In 63ae0915f8ec, I arranged to use a 32-bit rotate, without
> > considering the effect of a mask value that wraps around to
> > the high bits of the word.
>
> Thanks, that passes my tests.
>
> Tested-by: Anton Blanchard <anton@samba.org>
Unfortunately the earlier buggy version already got pulled upstream.
I've folded this new version with a revert of the earlier one and
merged to ppc-for-2.7.
>
> Anton
>
> > Signed-off-by: Richard Henderson <rth@twiddle.net>
> > ---
> > target-ppc/translate.c | 73
> > +++++++++++++++++++++++++++++++++++--------------- 1 file changed, 51
> > insertions(+), 22 deletions(-)
> >
> > diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> > index b689475..23bc054 100644
> > --- a/target-ppc/translate.c
> > +++ b/target-ppc/translate.c
> > @@ -1636,7 +1636,6 @@ static void gen_rlwimi(DisasContext *ctx)
> > tcg_gen_deposit_tl(t_ra, t_ra, t_rs, sh, me - mb + 1);
> > } else {
> > target_ulong mask;
> > - TCGv_i32 t0;
> > TCGv t1;
> >
> > #if defined(TARGET_PPC64)
> > @@ -1645,12 +1644,21 @@ static void gen_rlwimi(DisasContext *ctx)
> > #endif
> > mask = MASK(mb, me);
> >
> > - t0 = tcg_temp_new_i32();
> > t1 = tcg_temp_new();
> > - tcg_gen_trunc_tl_i32(t0, t_rs);
> > - tcg_gen_rotli_i32(t0, t0, sh);
> > - tcg_gen_extu_i32_tl(t1, t0);
> > - tcg_temp_free_i32(t0);
> > + if (mask <= 0xffffffffu) {
> > + TCGv_i32 t0 = tcg_temp_new_i32();
> > + tcg_gen_trunc_tl_i32(t0, t_rs);
> > + tcg_gen_rotli_i32(t0, t0, sh);
> > + tcg_gen_extu_i32_tl(t1, t0);
> > + tcg_temp_free_i32(t0);
> > + } else {
> > +#if defined(TARGET_PPC64)
> > + tcg_gen_deposit_i64(t1, t_rs, t_rs, 32, 32);
> > + tcg_gen_rotli_i64(t1, t1, sh);
> > +#else
> > + g_assert_not_reached();
> > +#endif
> > + }
> >
> > tcg_gen_andi_tl(t1, t1, mask);
> > tcg_gen_andi_tl(t_ra, t_ra, ~mask);
> > @@ -1678,20 +1686,28 @@ static void gen_rlwinm(DisasContext *ctx)
> > tcg_gen_ext32u_tl(t_ra, t_rs);
> > tcg_gen_shri_tl(t_ra, t_ra, mb);
> > } else {
> > + target_ulong mask;
> > #if defined(TARGET_PPC64)
> > mb += 32;
> > me += 32;
> > #endif
> > - if (sh == 0) {
> > - tcg_gen_andi_tl(t_ra, t_rs, MASK(mb, me));
> > - } else {
> > - TCGv_i32 t0 = tcg_temp_new_i32();
> > + mask = MASK(mb, me);
> >
> > + if (mask <= 0xffffffffu) {
> > + TCGv_i32 t0 = tcg_temp_new_i32();
> > tcg_gen_trunc_tl_i32(t0, t_rs);
> > tcg_gen_rotli_i32(t0, t0, sh);
> > - tcg_gen_andi_i32(t0, t0, MASK(mb, me));
> > + tcg_gen_andi_i32(t0, t0, mask);
> > tcg_gen_extu_i32_tl(t_ra, t0);
> > tcg_temp_free_i32(t0);
> > + } else {
> > +#if defined(TARGET_PPC64)
> > + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
> > + tcg_gen_rotli_i64(t_ra, t_ra, sh);
> > + tcg_gen_andi_i64(t_ra, t_ra, mask);
> > +#else
> > + g_assert_not_reached();
> > +#endif
> > }
> > }
> > if (unlikely(Rc(ctx->opcode) != 0)) {
> > @@ -1707,24 +1723,37 @@ static void gen_rlwnm(DisasContext *ctx)
> > TCGv t_rb = cpu_gpr[rB(ctx->opcode)];
> > uint32_t mb = MB(ctx->opcode);
> > uint32_t me = ME(ctx->opcode);
> > - TCGv_i32 t0, t1;
> > + target_ulong mask;
> >
> > #if defined(TARGET_PPC64)
> > mb += 32;
> > me += 32;
> > #endif
> > + mask = MASK(mb, me);
> >
> > - t0 = tcg_temp_new_i32();
> > - t1 = tcg_temp_new_i32();
> > - tcg_gen_trunc_tl_i32(t0, t_rb);
> > - tcg_gen_trunc_tl_i32(t1, t_rs);
> > - tcg_gen_andi_i32(t0, t0, 0x1f);
> > - tcg_gen_rotl_i32(t1, t1, t0);
> > - tcg_temp_free_i32(t0);
> > + if (mask <= 0xffffffffu) {
> > + TCGv_i32 t0 = tcg_temp_new_i32();
> > + TCGv_i32 t1 = tcg_temp_new_i32();
> > + tcg_gen_trunc_tl_i32(t0, t_rb);
> > + tcg_gen_trunc_tl_i32(t1, t_rs);
> > + tcg_gen_andi_i32(t0, t0, 0x1f);
> > + tcg_gen_rotl_i32(t1, t1, t0);
> > + tcg_gen_extu_i32_tl(t_ra, t1);
> > + tcg_temp_free_i32(t0);
> > + tcg_temp_free_i32(t1);
> > + } else {
> > +#if defined(TARGET_PPC64)
> > + TCGv_i64 t0 = tcg_temp_new_i64();
> > + tcg_gen_andi_i64(t0, t_rb, 0x1f);
> > + tcg_gen_deposit_i64(t_ra, t_rs, t_rs, 32, 32);
> > + tcg_gen_rotl_i64(t_ra, t_ra, t0);
> > + tcg_temp_free_i64(t0);
> > +#else
> > + g_assert_not_reached();
> > +#endif
> > + }
> >
> > - tcg_gen_andi_i32(t1, t1, MASK(mb, me));
> > - tcg_gen_extu_i32_tl(t_ra, t1);
> > - tcg_temp_free_i32(t1);
> > + tcg_gen_andi_tl(t_ra, t_ra, mask);
> >
> > if (unlikely(Rc(ctx->opcode) != 0)) {
> > gen_set_Rc0(ctx, t_ra);
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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2016-06-18 5:19 [Qemu-devel] [PATCH v2] target-ppc: Fix rlwimi, rlwinm, rlwnm Richard Henderson
2016-06-18 17:34 ` Anton Blanchard
2016-06-20 2:12 ` David Gibson
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