From: "Michael S. Tsirkin" <mst@redhat.com>
To: Andrea Arcangeli <aarcange@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>,
Eduardo Habkost <ehabkost@redhat.com>,
Marcel Apfelbaum <marcel@redhat.com>,
"Dr. David Alan Gilbert" <dgilbert@redhat.com>,
qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] Default for phys-addr-bits? (was Re: [PATCH 4/5] x86: Allow physical address bits to be set)
Date: Thu, 23 Jun 2016 02:45:24 +0300 [thread overview]
Message-ID: <20160623024400-mutt-send-email-mst@redhat.com> (raw)
In-Reply-To: <20160622232308.GQ30202@redhat.com>
On Thu, Jun 23, 2016 at 01:23:08AM +0200, Andrea Arcangeli wrote:
> On Thu, Jun 23, 2016 at 01:44:06AM +0300, Michael S. Tsirkin wrote:
> > On Wed, Jun 22, 2016 at 04:24:14PM +0200, Andrea Arcangeli wrote:
> > > > cause malfunctioning, only crashes (and as Gerd said, if you cross your
> > > > fingers and hope the guest doesn't put anything so high in memory,
> > > > chances are you'll succeed), and this makes it "safer". I'm not sure
> > > > which one is more likely to happen.
> > >
> > > But the crash with guest phys bits > host phys bits is material, linux
> > > will definitely crash in such condition.
> >
> > Why would it? Most GPA addresses are not guest controllable.
> > Don't give guest addresses that host can't access, you will not get
> > a crash.
> >
> > The only exception I know of is PCI BARs but we can limit
> > these to a safe addressable range using _CRS method in ACPI.
> >
> > Could you explain please?
>
> Well the crash of guest phys bits > host phys bits, should be easy to
> reproduce by booting a 65GB guest on a 64GB RAM + 2GB swap host with
> 36 host phys bits using the upstream qemu that forces the guest phys
> bits to 40.
So you supply more RAM than host can address, and guest crashes?
Why are we worried about it?
I would say that's a management bug.
> Likely the guest won't boot properly regardless if the PCI bars are at
> the end, but it may have a chance to print something meaningful on the
> console while trying instead of failing in some unexpected way.
>
> Now the production patch fixes it 100% by using the host bits instead
> of value 40. However you'd run into the instability if you migrate the
> same guest to the aformentioned host.
>
> No amount of guest changes can fix the above. So then we can avoid any
> risk of breakages also during live migration introducing a "soft"
> guest phys bits set as low as possible. And live migration restore can
> check it against the host phys bits.
I don't think it's worth fixing. Just don't give more RAM than
host can address.
> The other case (guest phys bits < host phys bits) instead requires a
> guest doing something strange, definitely never going to be a problem
> with linux as guest at least.
next prev parent reply other threads:[~2016-06-22 23:45 UTC|newest]
Thread overview: 73+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-06-16 17:12 [Qemu-devel] [PATCH 0/5] x86: Physical address limit patches Dr. David Alan Gilbert (git)
2016-06-16 17:12 ` [Qemu-devel] [PATCH 1/5] BIT_RANGE convenience macro Dr. David Alan Gilbert (git)
2016-06-16 17:23 ` Paolo Bonzini
2016-06-16 17:24 ` Dr. David Alan Gilbert
2016-06-16 18:01 ` Peter Maydell
2016-06-16 18:05 ` Paolo Bonzini
2016-06-20 14:11 ` Dr. David Alan Gilbert
2016-06-20 14:17 ` Peter Maydell
2016-06-16 17:12 ` [Qemu-devel] [PATCH 2/5] x86: Mask mtrr mask based on CPU physical address limits Dr. David Alan Gilbert (git)
2016-06-16 19:59 ` Eduardo Habkost
2016-06-17 8:23 ` Dr. David Alan Gilbert
2016-06-17 12:13 ` Paolo Bonzini
2016-06-16 17:12 ` [Qemu-devel] [PATCH 3/5] x86: fill high bits of mtrr mask Dr. David Alan Gilbert (git)
2016-06-16 20:14 ` Eduardo Habkost
2016-06-17 7:47 ` Paolo Bonzini
2016-06-17 12:46 ` Eduardo Habkost
2016-06-17 13:01 ` Paolo Bonzini
2016-06-17 13:41 ` Eduardo Habkost
2016-06-17 14:25 ` Paolo Bonzini
2016-06-17 15:27 ` Eduardo Habkost
2016-06-17 15:29 ` Paolo Bonzini
2016-06-17 15:35 ` Eduardo Habkost
2016-06-17 13:51 ` Dr. David Alan Gilbert
2016-06-17 14:19 ` Paolo Bonzini
2016-06-17 8:53 ` Dr. David Alan Gilbert
2016-06-16 17:12 ` [Qemu-devel] [PATCH 4/5] x86: Allow physical address bits to be set Dr. David Alan Gilbert (git)
2016-06-16 17:26 ` Paolo Bonzini
2016-06-16 18:09 ` Eduardo Habkost
2016-06-16 20:24 ` Eduardo Habkost
2016-06-17 8:15 ` Dr. David Alan Gilbert
2016-06-17 8:43 ` Paolo Bonzini
2016-06-17 9:17 ` Gerd Hoffmann
2016-06-17 9:52 ` Igor Mammedov
2016-06-17 11:20 ` Gerd Hoffmann
2016-06-17 16:20 ` Laszlo Ersek
2016-06-17 16:07 ` Laszlo Ersek
2016-06-19 16:13 ` Marcel Apfelbaum
2016-06-20 10:42 ` Igor Mammedov
2016-06-20 11:13 ` Marcel Apfelbaum
2016-06-17 9:37 ` Dr. David Alan Gilbert
2016-06-17 9:54 ` Paolo Bonzini
2016-06-17 13:18 ` Eduardo Habkost
2016-06-17 13:38 ` Paolo Bonzini
2016-06-17 15:19 ` Eduardo Habkost
2016-06-17 15:28 ` Paolo Bonzini
2016-06-17 15:49 ` Eduardo Habkost
2016-06-21 19:44 ` [Qemu-devel] Default for phys-addr-bits? (was Re: [PATCH 4/5] x86: Allow physical address bits to be set) Eduardo Habkost
2016-06-22 12:41 ` Paolo Bonzini
2016-06-22 14:24 ` Andrea Arcangeli
2016-06-22 14:33 ` Paolo Bonzini
2016-06-22 14:44 ` Andrea Arcangeli
2016-06-22 14:48 ` Paolo Bonzini
2016-06-22 15:02 ` Andrea Arcangeli
2016-06-22 22:44 ` Michael S. Tsirkin
2016-06-22 23:23 ` Andrea Arcangeli
2016-06-22 23:45 ` Michael S. Tsirkin [this message]
2016-06-23 8:40 ` Gerd Hoffmann
2016-06-23 16:38 ` Michael S. Tsirkin
2016-06-24 5:55 ` Gerd Hoffmann
2016-06-24 23:12 ` Michael S. Tsirkin
2016-06-29 16:42 ` Dr. David Alan Gilbert
2016-06-30 6:10 ` Gerd Hoffmann
2016-06-30 10:59 ` Dr. David Alan Gilbert
2016-06-30 16:14 ` Gerd Hoffmann
2016-06-30 17:12 ` Dr. David Alan Gilbert
2016-07-01 19:03 ` Dr. David Alan Gilbert
2016-06-22 22:40 ` Michael S. Tsirkin
2016-06-22 23:15 ` Andrea Arcangeli
2016-06-19 3:36 ` [Qemu-devel] [PATCH 4/5] x86: Allow physical address bits to be set Michael S. Tsirkin
2016-06-20 7:04 ` Paolo Bonzini
2016-06-17 14:24 ` Marcel Apfelbaum
2016-06-16 17:12 ` [Qemu-devel] [PATCH 5/5] x86: Set physical address bits based on host Dr. David Alan Gilbert (git)
2016-06-17 7:25 ` Igor Mammedov
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