From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47366) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bGJY3-0004TJ-QP for qemu-devel@nongnu.org; Fri, 24 Jun 2016 01:21:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bGJXz-0006oK-IS for qemu-devel@nongnu.org; Fri, 24 Jun 2016 01:20:59 -0400 Date: Fri, 24 Jun 2016 15:19:51 +1000 From: David Gibson Message-ID: <20160624051951.GI15625@voom.fritz.box> References: <1466704050-15108-1-git-send-email-nikunj@linux.vnet.ibm.com> <1466704050-15108-3-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="BWWlCdgt6QLN7tv3" Content-Disposition: inline In-Reply-To: <1466704050-15108-3-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org, Benjamin Herrenschmidt --BWWlCdgt6QLN7tv3 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jun 23, 2016 at 11:17:21PM +0530, Nikunj A Dadhania wrote: > From: Benjamin Herrenschmidt >=20 > Leave the core ICP/ICS logic in xics.c and move the top level > class wrapper, hypercall and RTAS handlers to xics_spapr.c >=20 > Signed-off-by: Benjamin Herrenschmidt > [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to > xics_spapr.c] > Signed-off-by: Nikunj A Dadhania > --- > default-configs/ppc64-softmmu.mak | 1 + > hw/intc/Makefile.objs | 1 + > hw/intc/xics.c | 418 +-------------------------------= ---- > hw/intc/xics_spapr.c | 432 ++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/xics.h | 21 ++ > 5 files changed, 464 insertions(+), 409 deletions(-) > create mode 100644 hw/intc/xics_spapr.c >=20 > diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-so= ftmmu.mak > index bb71b23..c4be59f 100644 > --- a/default-configs/ppc64-softmmu.mak > +++ b/default-configs/ppc64-softmmu.mak > @@ -49,6 +49,7 @@ CONFIG_ETSEC=3Dy > CONFIG_LIBDECNUMBER=3Dy > # For pSeries > CONFIG_XICS=3D$(CONFIG_PSERIES) > +CONFIG_XICS_SPAPR=3D$(CONFIG_PSERIES) > CONFIG_XICS_KVM=3D$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) > # For PReP > CONFIG_MC146818RTC=3Dy > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs > index c7bbf88..530df2e 100644 > --- a/hw/intc/Makefile.objs > +++ b/hw/intc/Makefile.objs > @@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) +=3D openpic_kvm.o > obj-$(CONFIG_RASPI) +=3D bcm2835_ic.o bcm2836_control.o > obj-$(CONFIG_SH4) +=3D sh_intc.o > obj-$(CONFIG_XICS) +=3D xics.o > +obj-$(CONFIG_XICS_SPAPR) +=3D xics_spapr.o > obj-$(CONFIG_XICS_KVM) +=3D xics_kvm.o > obj-$(CONFIG_ALLWINNER_A10_PIC) +=3D allwinner-a10-pic.o > obj-$(CONFIG_S390_FLIC) +=3D s390_flic.o > diff --git a/hw/intc/xics.c b/hw/intc/xics.c > index a715532..6ca391f 100644 > --- a/hw/intc/xics.c > +++ b/hw/intc/xics.c > @@ -32,12 +32,11 @@ > #include "hw/hw.h" > #include "trace.h" > #include "qemu/timer.h" > -#include "hw/ppc/spapr.h" > #include "hw/ppc/xics.h" > #include "qemu/error-report.h" > #include "qapi/visitor.h" > =20 > -static int get_cpu_index_by_dt_id(int cpu_dt_id) > +int get_cpu_index_by_dt_id(int cpu_dt_id) If this is made public it needs xics_*() name the current one is too generic for a global symbol. > { > PowerPCCPU *cpu =3D ppc_get_vcpu_by_dt_id(cpu_dt_id); > =20 > @@ -242,7 +241,7 @@ static void icp_resend(XICSState *icp, int server) > ics_resend(icp->ics); > } > =20 > -static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) > +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr) > { > ICPState *ss =3D icp->ss + server; > uint8_t old_cppr; > @@ -266,7 +265,7 @@ static void icp_set_cppr(XICSState *icp, int server, = uint8_t cppr) > } > } > =20 > -static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr) > +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr) > { > ICPState *ss =3D icp->ss + server; > =20 > @@ -276,7 +275,7 @@ static void icp_set_mfrr(XICSState *icp, int server, = uint8_t mfrr) > } > } > =20 > -static uint32_t icp_accept(ICPState *ss) > +uint32_t icp_accept(ICPState *ss) > { > uint32_t xirr =3D ss->xirr; > =20 > @@ -289,7 +288,7 @@ static uint32_t icp_accept(ICPState *ss) > return xirr; > } > =20 > -static void icp_eoi(XICSState *icp, int server, uint32_t xirr) > +void icp_eoi(XICSState *icp, int server, uint32_t xirr) > { > ICPState *ss =3D icp->ss + server; > =20 > @@ -390,12 +389,6 @@ static const TypeInfo icp_info =3D { > /* > * ICS: Source layer > */ > -static int ics_valid_irq(ICSState *ics, uint32_t nr) > -{ > - return (nr >=3D ics->offset) > - && (nr < (ics->offset + ics->nr_irqs)); > -} > - > static void resend_msi(ICSState *ics, int srcno) > { > ICSIRQState *irq =3D ics->irqs + srcno; > @@ -480,8 +473,8 @@ static void write_xive_lsi(ICSState *ics, int srcno) > resend_lsi(ics, srcno); > } > =20 > -static void ics_write_xive(ICSState *ics, int nr, int server, > - uint8_t priority, uint8_t saved_priority) > +void ics_write_xive(ICSState *ics, int nr, int server, > + uint8_t priority, uint8_t saved_priority) > { > int srcno =3D nr - ics->offset; > ICSIRQState *irq =3D ics->irqs + srcno; > @@ -658,7 +651,7 @@ static const TypeInfo ics_info =3D { > /* > * Exported functions > */ > -static int xics_find_source(XICSState *icp, int irq) > +int xics_find_source(XICSState *icp, int irq) > { > int sources =3D 1; > int src; > @@ -686,7 +679,7 @@ qemu_irq xics_get_qirq(XICSState *icp, int irq) > return NULL; > } > =20 > -static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) > +void ics_set_irq_type(ICSState *ics, int srcno, bool lsi) > { > assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK)); > =20 > @@ -705,402 +698,9 @@ void xics_set_irq_type(XICSState *icp, int irq, boo= l lsi) > ics_set_irq_type(ics, irq - ics->offset, lsi); > } > =20 > -#define ICS_IRQ_FREE(ics, srcno) \ > - (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) > - > -static int ics_find_free_block(ICSState *ics, int num, int alignnum) > -{ > - int first, i; > - > - for (first =3D 0; first < ics->nr_irqs; first +=3D alignnum) { > - if (num > (ics->nr_irqs - first)) { > - return -1; > - } > - for (i =3D first; i < first + num; ++i) { > - if (!ICS_IRQ_FREE(ics, i)) { > - break; > - } > - } > - if (i =3D=3D (first + num)) { > - return first; > - } > - } > - > - return -1; > -} > - > -int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi, > - Error **errp) > -{ > - ICSState *ics =3D &icp->ics[src]; > - int irq; > - > - if (irq_hint) { > - assert(src =3D=3D xics_find_source(icp, irq_hint)); > - if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { > - error_setg(errp, "can't allocate IRQ %d: already in use", ir= q_hint); > - return -1; > - } > - irq =3D irq_hint; > - } else { > - irq =3D ics_find_free_block(ics, 1, 1); > - if (irq < 0) { > - error_setg(errp, "can't allocate IRQ: no IRQ left"); > - return -1; > - } > - irq +=3D ics->offset; > - } > - > - ics_set_irq_type(ics, irq - ics->offset, lsi); > - trace_xics_alloc(src, irq); > - > - return irq; > -} > - > -/* > - * Allocate block of consecutive IRQs, and return the number of the firs= t IRQ in the block. > - * If align=3D=3Dtrue, aligns the first IRQ number to num. > - */ > -int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, > - bool align, Error **errp) > -{ > - int i, first =3D -1; > - ICSState *ics =3D &icp->ics[src]; > - > - assert(src =3D=3D 0); > - /* > - * MSIMesage::data is used for storing VIRQ so > - * it has to be aligned to num to support multiple > - * MSI vectors. MSI-X is not affected by this. > - * The hint is used for the first IRQ, the rest should > - * be allocated continuously. > - */ > - if (align) { > - assert((num =3D=3D 1) || (num =3D=3D 2) || (num =3D=3D 4) || > - (num =3D=3D 8) || (num =3D=3D 16) || (num =3D=3D 32)); > - first =3D ics_find_free_block(ics, num, num); > - } else { > - first =3D ics_find_free_block(ics, num, 1); > - } > - if (first < 0) { > - error_setg(errp, "can't find a free %d-IRQ block", num); > - return -1; > - } > - > - if (first >=3D 0) { > - for (i =3D first; i < first + num; ++i) { > - ics_set_irq_type(ics, i, lsi); > - } > - } > - first +=3D ics->offset; > - > - trace_xics_alloc_block(src, first, num, lsi, align); > - > - return first; > -} > - > -static void ics_free(ICSState *ics, int srcno, int num) > -{ > - int i; > - > - for (i =3D srcno; i < srcno + num; ++i) { > - if (ICS_IRQ_FREE(ics, i)) { > - trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offse= t); > - } > - memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); > - } > -} > - > -void xics_spapr_free(XICSState *icp, int irq, int num) > -{ > - int src =3D xics_find_source(icp, irq); > - > - if (src >=3D 0) { > - ICSState *ics =3D &icp->ics[src]; > - > - /* FIXME: implement multiple sources */ > - assert(src =3D=3D 0); > - > - trace_xics_ics_free(ics - icp->ics, irq, num); > - ics_free(ics, irq - ics->offset, num); > - } > -} > - > -/* > - * Guest interfaces > - */ > - > -static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - CPUState *cs =3D CPU(cpu); > - target_ulong cppr =3D args[0]; > - > - icp_set_cppr(spapr->icp, cs->cpu_index, cppr); > - return H_SUCCESS; > -} > - > -static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - target_ulong server =3D get_cpu_index_by_dt_id(args[0]); > - target_ulong mfrr =3D args[1]; > - > - if (server >=3D spapr->icp->nr_servers) { > - return H_PARAMETER; > - } > - > - icp_set_mfrr(spapr->icp, server, mfrr); > - return H_SUCCESS; > -} > - > -static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - CPUState *cs =3D CPU(cpu); > - uint32_t xirr =3D icp_accept(spapr->icp->ss + cs->cpu_index); > - > - args[0] =3D xirr; > - return H_SUCCESS; > -} > - > -static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - CPUState *cs =3D CPU(cpu); > - ICPState *ss =3D &spapr->icp->ss[cs->cpu_index]; > - uint32_t xirr =3D icp_accept(ss); > - > - args[0] =3D xirr; > - args[1] =3D cpu_get_host_ticks(); > - return H_SUCCESS; > -} > - > -static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - CPUState *cs =3D CPU(cpu); > - target_ulong xirr =3D args[0]; > - > - icp_eoi(spapr->icp, cs->cpu_index, xirr); > - return H_SUCCESS; > -} > - > -static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - target_ulong opcode, target_ulong *args) > -{ > - CPUState *cs =3D CPU(cpu); > - ICPState *ss =3D &spapr->icp->ss[cs->cpu_index]; > - > - args[0] =3D ss->xirr; > - args[1] =3D ss->mfrr; > - > - return H_SUCCESS; > -} > - > -static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - uint32_t token, > - uint32_t nargs, target_ulong args, > - uint32_t nret, target_ulong rets) > -{ > - ICSState *ics =3D spapr->icp->ics; > - uint32_t nr, server, priority; > - > - if ((nargs !=3D 3) || (nret !=3D 1)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - nr =3D rtas_ld(args, 0); > - server =3D get_cpu_index_by_dt_id(rtas_ld(args, 1)); > - priority =3D rtas_ld(args, 2); > - > - if (!ics_valid_irq(ics, nr) || (server >=3D ics->icp->nr_servers) > - || (priority > 0xff)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - ics_write_xive(ics, nr, server, priority, priority); > - > - rtas_st(rets, 0, RTAS_OUT_SUCCESS); > -} > - > -static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - uint32_t token, > - uint32_t nargs, target_ulong args, > - uint32_t nret, target_ulong rets) > -{ > - ICSState *ics =3D spapr->icp->ics; > - uint32_t nr; > - > - if ((nargs !=3D 1) || (nret !=3D 3)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - nr =3D rtas_ld(args, 0); > - > - if (!ics_valid_irq(ics, nr)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - rtas_st(rets, 0, RTAS_OUT_SUCCESS); > - rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); > - rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); > -} > - > -static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - uint32_t token, > - uint32_t nargs, target_ulong args, > - uint32_t nret, target_ulong rets) > -{ > - ICSState *ics =3D spapr->icp->ics; > - uint32_t nr; > - > - if ((nargs !=3D 1) || (nret !=3D 1)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - nr =3D rtas_ld(args, 0); > - > - if (!ics_valid_irq(ics, nr)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, > - ics->irqs[nr - ics->offset].priority); > - > - rtas_st(rets, 0, RTAS_OUT_SUCCESS); > -} > - > -static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr, > - uint32_t token, > - uint32_t nargs, target_ulong args, > - uint32_t nret, target_ulong rets) > -{ > - ICSState *ics =3D spapr->icp->ics; > - uint32_t nr; > - > - if ((nargs !=3D 1) || (nret !=3D 1)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - nr =3D rtas_ld(args, 0); > - > - if (!ics_valid_irq(ics, nr)) { > - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > - return; > - } > - > - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, > - ics->irqs[nr - ics->offset].saved_priority, > - ics->irqs[nr - ics->offset].saved_priority); > - > - rtas_st(rets, 0, RTAS_OUT_SUCCESS); > -} > - > -/* > - * XICS > - */ > - > -static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **e= rrp) > -{ > - icp->nr_irqs =3D icp->ics->nr_irqs =3D nr_irqs; > -} > - > -static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers, > - Error **errp) > -{ > - int i; > - > - icp->nr_servers =3D nr_servers; > - > - icp->ss =3D g_malloc0(icp->nr_servers*sizeof(ICPState)); > - for (i =3D 0; i < icp->nr_servers; i++) { > - char buffer[32]; > - object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); > - snprintf(buffer, sizeof(buffer), "icp[%d]", i); > - object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i= ]), > - errp); > - } > -} > - > -static void xics_spapr_realize(DeviceState *dev, Error **errp) > -{ > - XICSState *icp =3D XICS(dev); > - Error *error =3D NULL; > - int i; > - > - if (!icp->nr_servers) { > - error_setg(errp, "Number of servers needs to be greater 0"); > - return; > - } > - > - /* Registration of global state belongs into realize */ > - spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive= ); > - spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive= ); > - spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); > - spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); > - > - spapr_register_hypercall(H_CPPR, h_cppr); > - spapr_register_hypercall(H_IPI, h_ipi); > - spapr_register_hypercall(H_XIRR, h_xirr); > - spapr_register_hypercall(H_XIRR_X, h_xirr_x); > - spapr_register_hypercall(H_EOI, h_eoi); > - spapr_register_hypercall(H_IPOLL, h_ipoll); > - > - object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); > - if (error) { > - error_propagate(errp, error); > - return; > - } > - > - for (i =3D 0; i < icp->nr_servers; i++) { > - object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", = &error); > - if (error) { > - error_propagate(errp, error); > - return; > - } > - } > -} > - > -static void xics_spapr_initfn(Object *obj) > -{ > - XICSState *xics =3D XICS(obj); > - > - xics->ics =3D ICS(object_new(TYPE_ICS)); > - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); > - xics->ics->icp =3D xics; > -} > - > -static void xics_spapr_class_init(ObjectClass *oc, void *data) > -{ > - DeviceClass *dc =3D DEVICE_CLASS(oc); > - XICSStateClass *xsc =3D XICS_SPAPR_CLASS(oc); > - > - dc->realize =3D xics_spapr_realize; > - xsc->set_nr_irqs =3D xics_set_nr_irqs; > - xsc->set_nr_servers =3D xics_set_nr_servers; > -} > - > -static const TypeInfo xics_spapr_info =3D { > - .name =3D TYPE_XICS_SPAPR, > - .parent =3D TYPE_XICS_COMMON, > - .instance_size =3D sizeof(XICSState), > - .class_size =3D sizeof(XICSStateClass), > - .class_init =3D xics_spapr_class_init, > - .instance_init =3D xics_spapr_initfn, > -}; > - > static void xics_register_types(void) > { > type_register_static(&xics_common_info); > - type_register_static(&xics_spapr_info); > type_register_static(&ics_info); > type_register_static(&icp_info); > } > diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c > new file mode 100644 > index 0000000..48d458a > --- /dev/null > +++ b/hw/intc/xics_spapr.c > @@ -0,0 +1,432 @@ > +/* > + * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Em= ulator > + * > + * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics > + * > + * Copyright (c) 2010,2011 David Gibson, IBM Corporation. > + * > + * Permission is hereby granted, free of charge, to any person obtaining= a copy > + * of this software and associated documentation files (the "Software"),= to deal > + * in the Software without restriction, including without limitation the= rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be includ= ed in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN > + * THE SOFTWARE. > + * > + */ > + > +#include "qemu/osdep.h" > +#include "cpu.h" > +#include "hw/hw.h" > +#include "trace.h" > +#include "qemu/timer.h" > +#include "hw/ppc/spapr.h" > +#include "hw/ppc/xics.h" > +#include "qapi/visitor.h" > +#include "qapi/error.h" > + > +/* > + * Guest interfaces > + */ > + > +static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + CPUState *cs =3D CPU(cpu); > + target_ulong cppr =3D args[0]; > + > + icp_set_cppr(spapr->icp, cs->cpu_index, cppr); > + return H_SUCCESS; > +} > + > +static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + target_ulong server =3D get_cpu_index_by_dt_id(args[0]); > + target_ulong mfrr =3D args[1]; > + > + if (server >=3D spapr->icp->nr_servers) { > + return H_PARAMETER; > + } > + > + icp_set_mfrr(spapr->icp, server, mfrr); > + return H_SUCCESS; > +} > + > +static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + CPUState *cs =3D CPU(cpu); > + uint32_t xirr =3D icp_accept(spapr->icp->ss + cs->cpu_index); > + > + args[0] =3D xirr; > + return H_SUCCESS; > +} > + > +static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + CPUState *cs =3D CPU(cpu); > + ICPState *ss =3D &spapr->icp->ss[cs->cpu_index]; > + uint32_t xirr =3D icp_accept(ss); > + > + args[0] =3D xirr; > + args[1] =3D cpu_get_host_ticks(); > + return H_SUCCESS; > +} > + > +static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + CPUState *cs =3D CPU(cpu); > + target_ulong xirr =3D args[0]; > + > + icp_eoi(spapr->icp, cs->cpu_index, xirr); > + return H_SUCCESS; > +} > + > +static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + target_ulong opcode, target_ulong *args) > +{ > + CPUState *cs =3D CPU(cpu); > + ICPState *ss =3D &spapr->icp->ss[cs->cpu_index]; > + > + args[0] =3D ss->xirr; > + args[1] =3D ss->mfrr; > + > + return H_SUCCESS; > +} > + > +static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + uint32_t token, > + uint32_t nargs, target_ulong args, > + uint32_t nret, target_ulong rets) > +{ > + ICSState *ics =3D spapr->icp->ics; > + uint32_t nr, server, priority; > + > + if ((nargs !=3D 3) || (nret !=3D 1)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + nr =3D rtas_ld(args, 0); > + server =3D get_cpu_index_by_dt_id(rtas_ld(args, 1)); > + priority =3D rtas_ld(args, 2); > + > + if (!ics_valid_irq(ics, nr) || (server >=3D ics->icp->nr_servers) > + || (priority > 0xff)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + ics_write_xive(ics, nr, server, priority, priority); > + > + rtas_st(rets, 0, RTAS_OUT_SUCCESS); > +} > + > +static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + uint32_t token, > + uint32_t nargs, target_ulong args, > + uint32_t nret, target_ulong rets) > +{ > + ICSState *ics =3D spapr->icp->ics; > + uint32_t nr; > + > + if ((nargs !=3D 1) || (nret !=3D 3)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + nr =3D rtas_ld(args, 0); > + > + if (!ics_valid_irq(ics, nr)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + rtas_st(rets, 0, RTAS_OUT_SUCCESS); > + rtas_st(rets, 1, ics->irqs[nr - ics->offset].server); > + rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority); > +} > + > +static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + uint32_t token, > + uint32_t nargs, target_ulong args, > + uint32_t nret, target_ulong rets) > +{ > + ICSState *ics =3D spapr->icp->ics; > + uint32_t nr; > + > + if ((nargs !=3D 1) || (nret !=3D 1)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + nr =3D rtas_ld(args, 0); > + > + if (!ics_valid_irq(ics, nr)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff, > + ics->irqs[nr - ics->offset].priority); > + > + rtas_st(rets, 0, RTAS_OUT_SUCCESS); > +} > + > +static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr, > + uint32_t token, > + uint32_t nargs, target_ulong args, > + uint32_t nret, target_ulong rets) > +{ > + ICSState *ics =3D spapr->icp->ics; > + uint32_t nr; > + > + if ((nargs !=3D 1) || (nret !=3D 1)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + nr =3D rtas_ld(args, 0); > + > + if (!ics_valid_irq(ics, nr)) { > + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR); > + return; > + } > + > + ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, > + ics->irqs[nr - ics->offset].saved_priority, > + ics->irqs[nr - ics->offset].saved_priority); > + > + rtas_st(rets, 0, RTAS_OUT_SUCCESS); > +} > + > +static void xics_spapr_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, > + Error **errp) > +{ > + icp->nr_irqs =3D icp->ics->nr_irqs =3D nr_irqs; > +} > + > +static void xics_spapr_set_nr_servers(XICSState *icp, uint32_t nr_server= s, > + Error **errp) > +{ > + int i; > + > + icp->nr_servers =3D nr_servers; > + > + icp->ss =3D g_malloc0(icp->nr_servers * sizeof(ICPState)); > + for (i =3D 0; i < icp->nr_servers; i++) { > + char buffer[32]; > + object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP); > + snprintf(buffer, sizeof(buffer), "icp[%d]", i); > + object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i= ]), > + errp); > + } > +} > + > +static void xics_spapr_realize(DeviceState *dev, Error **errp) > +{ > + XICSState *icp =3D XICS(dev); > + Error *error =3D NULL; > + int i; > + > + if (!icp->nr_servers) { > + error_setg(errp, "Number of servers needs to be greater 0"); > + return; > + } > + > + /* Registration of global state belongs into realize */ > + spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive= ); > + spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive= ); > + spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off); > + spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on); > + > + spapr_register_hypercall(H_CPPR, h_cppr); > + spapr_register_hypercall(H_IPI, h_ipi); > + spapr_register_hypercall(H_XIRR, h_xirr); > + spapr_register_hypercall(H_XIRR_X, h_xirr_x); > + spapr_register_hypercall(H_EOI, h_eoi); > + spapr_register_hypercall(H_IPOLL, h_ipoll); > + > + object_property_set_bool(OBJECT(icp->ics), true, "realized", &error); > + if (error) { > + error_propagate(errp, error); > + return; > + } > + > + for (i =3D 0; i < icp->nr_servers; i++) { > + object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", = &error); > + if (error) { > + error_propagate(errp, error); > + return; > + } > + } > +} > + > +static void xics_spapr_initfn(Object *obj) > +{ > + XICSState *xics =3D XICS(obj); > + > + xics->ics =3D ICS(object_new(TYPE_ICS)); > + object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL); > + xics->ics->icp =3D xics; > +} > + > +static void xics_spapr_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + XICSStateClass *xsc =3D XICS_SPAPR_CLASS(oc); > + > + dc->realize =3D xics_spapr_realize; > + xsc->set_nr_irqs =3D xics_spapr_set_nr_irqs; > + xsc->set_nr_servers =3D xics_spapr_set_nr_servers; > +} > + > +static const TypeInfo xics_spapr_info =3D { > + .name =3D TYPE_XICS_SPAPR, > + .parent =3D TYPE_XICS_COMMON, > + .instance_size =3D sizeof(XICSState), > + .class_size =3D sizeof(XICSStateClass), > + .class_init =3D xics_spapr_class_init, > + .instance_init =3D xics_spapr_initfn, > +}; > + > +#define ICS_IRQ_FREE(ics, srcno) \ > + (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK))) > + > +static int ics_find_free_block(ICSState *ics, int num, int alignnum) > +{ > + int first, i; > + > + for (first =3D 0; first < ics->nr_irqs; first +=3D alignnum) { > + if (num > (ics->nr_irqs - first)) { > + return -1; > + } > + for (i =3D first; i < first + num; ++i) { > + if (!ICS_IRQ_FREE(ics, i)) { > + break; > + } > + } > + if (i =3D=3D (first + num)) { > + return first; > + } > + } > + > + return -1; > +} > + > +int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi, > + Error **errp) > +{ > + ICSState *ics =3D &icp->ics[src]; > + int irq; > + > + if (irq_hint) { > + assert(src =3D=3D xics_find_source(icp, irq_hint)); > + if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) { > + error_setg(errp, "can't allocate IRQ %d: already in use", ir= q_hint); > + return -1; > + } > + irq =3D irq_hint; > + } else { > + irq =3D ics_find_free_block(ics, 1, 1); > + if (irq < 0) { > + error_setg(errp, "can't allocate IRQ: no IRQ left"); > + return -1; > + } > + irq +=3D ics->offset; > + } > + > + ics_set_irq_type(ics, irq - ics->offset, lsi); > + trace_xics_alloc(src, irq); > + > + return irq; > +} > + > +/* > + * Allocate block of consecutive IRQs, and return the number of the firs= t IRQ in > + * the block. If align=3D=3Dtrue, aligns the first IRQ number to num. > + */ > +int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi, > + bool align, Error **errp) > +{ > + int i, first =3D -1; > + ICSState *ics =3D &icp->ics[src]; > + > + assert(src =3D=3D 0); > + /* > + * MSIMesage::data is used for storing VIRQ so > + * it has to be aligned to num to support multiple > + * MSI vectors. MSI-X is not affected by this. > + * The hint is used for the first IRQ, the rest should > + * be allocated continuously. > + */ > + if (align) { > + assert((num =3D=3D 1) || (num =3D=3D 2) || (num =3D=3D 4) || > + (num =3D=3D 8) || (num =3D=3D 16) || (num =3D=3D 32)); > + first =3D ics_find_free_block(ics, num, num); > + } else { > + first =3D ics_find_free_block(ics, num, 1); > + } > + if (first < 0) { > + error_setg(errp, "can't find a free %d-IRQ block", num); > + return -1; > + } > + > + if (first >=3D 0) { > + for (i =3D first; i < first + num; ++i) { > + ics_set_irq_type(ics, i, lsi); > + } > + } > + first +=3D ics->offset; > + > + trace_xics_alloc_block(src, first, num, lsi, align); > + > + return first; > +} > + > +static void ics_free(ICSState *ics, int srcno, int num) > +{ > + int i; > + > + for (i =3D srcno; i < srcno + num; ++i) { > + if (ICS_IRQ_FREE(ics, i)) { > + trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offse= t); > + } > + memset(&ics->irqs[i], 0, sizeof(ICSIRQState)); > + } > +} > + > +void xics_spapr_free(XICSState *icp, int irq, int num) > +{ > + int src =3D xics_find_source(icp, irq); > + > + if (src >=3D 0) { > + ICSState *ics =3D &icp->ics[src]; > + > + /* FIXME: implement multiple sources */ > + assert(src =3D=3D 0); > + > + trace_xics_ics_free(ics - icp->ics, irq, num); > + ics_free(ics, irq - ics->offset, num); > + } > +} > + > +static void xics_spapr_register_types(void) > +{ > + type_register_static(&xics_spapr_info); > +} > + > +type_init(xics_spapr_register_types) > diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h > index 452a978..76b45ef 100644 > --- a/include/hw/ppc/xics.h > +++ b/include/hw/ppc/xics.h > @@ -145,6 +145,12 @@ struct ICSState { > XICSState *icp; > }; > =20 > +static inline bool ics_valid_irq(ICSState *ics, uint32_t nr) > +{ > + return (nr >=3D ics->offset) > + && (nr < (ics->offset + ics->nr_irqs)); > +} > + > struct ICSIRQState { > uint32_t server; > uint8_t priority; > @@ -174,4 +180,19 @@ void xics_spapr_free(XICSState *icp, int irq, int nu= m); > void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); > void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu); > =20 > +/* Internal XICS interfaces */ > +int get_cpu_index_by_dt_id(int cpu_dt_id); > + > +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr); > +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr); > +uint32_t icp_accept(ICPState *ss); > +void icp_eoi(XICSState *icp, int server, uint32_t xirr); > + > +void ics_write_xive(ICSState *ics, int nr, int server, > + uint8_t priority, uint8_t saved_priority); > + > +void ics_set_irq_type(ICSState *ics, int srcno, bool lsi); > + > +int xics_find_source(XICSState *icp, int irq); > + > #endif /* __XICS_H__ */ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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