* [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup
@ 2016-06-23 17:47 Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr Nikunj A Dadhania
` (10 more replies)
0 siblings, 11 replies; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj
sPAPR xics related changes required for powernv platform. This brings
infrastructure to get the xics native mode for powernv. Tested pseries guests
in KVM and TCG mode.
Some ToDos pending in patch 6:
+ xics_spapr_alloc - getting rid of that
+ xirr_owner - how to reassign after migration
Benjamin Herrenschmidt (11):
ppc/xics: Rename existing xics to xics_spapr
ppc/xics: Move SPAPR specific code to a separate file
ppc/xics: Implement H_IPOLL using an accessor
ppc/xics: Remove unused xics_set_irq_type()
ppc/xics: Replace "icp" with "xics" in most places
ppc/xics: Make the ICSState a list
ppc/xics: An ICS with offset 0 is assumed to be uninitialized
ppc/xics: Use a helper to add a new ICS
ppc/xics: Split ICS into ics-base and ics class
ppc/xics: Add "native" XICS subclass
ppc/xics: Add xics to the monitor "info pic" command
default-configs/ppc64-softmmu.mak | 4 +-
hmp-commands-info.hx | 2 +
hw/intc/Makefile.objs | 2 +
hw/intc/xics.c | 713 +++++++++++---------------------------
hw/intc/xics_kvm.c | 86 +++--
hw/intc/xics_native.c | 295 ++++++++++++++++
hw/intc/xics_spapr.c | 445 ++++++++++++++++++++++++
hw/ppc/ppc.c | 14 +
hw/ppc/spapr.c | 19 +-
hw/ppc/spapr_cpu_core.c | 4 +-
hw/ppc/spapr_events.c | 8 +-
hw/ppc/spapr_pci.c | 12 +-
hw/ppc/spapr_vio.c | 2 +-
include/hw/pci-host/spapr.h | 2 +-
include/hw/ppc/ppc.h | 1 +
include/hw/ppc/spapr.h | 2 +-
include/hw/ppc/spapr_vio.h | 2 +-
include/hw/ppc/xics.h | 83 ++++-
monitor.c | 4 +
19 files changed, 1113 insertions(+), 587 deletions(-)
create mode 100644 hw/intc/xics_native.c
create mode 100644 hw/intc/xics_spapr.c
--
2.7.4
^ permalink raw reply [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-24 5:17 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file Nikunj A Dadhania
` (9 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The common class doesn't change, the KVM one is sPAPR specific. Rename
variables and functions to xics_spapr.
Retain the type name as "xics" to preserve migration for existing sPAPR
guests.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 29 +++++++++++++++--------------
hw/intc/xics_kvm.c | 6 +++---
hw/ppc/spapr.c | 7 ++++---
hw/ppc/spapr_events.c | 2 +-
hw/ppc/spapr_pci.c | 10 +++++-----
hw/ppc/spapr_vio.c | 2 +-
include/hw/ppc/xics.h | 29 +++++++++++++++++------------
7 files changed, 46 insertions(+), 39 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index cce7f3d..a715532 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -729,7 +729,8 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
return -1;
}
-int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)
+int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
+ Error **errp)
{
ICSState *ics = &icp->ics[src];
int irq;
@@ -760,8 +761,8 @@ int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)
* Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
* If align==true, aligns the first IRQ number to num.
*/
-int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
- Error **errp)
+int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
+ bool align, Error **errp)
{
int i, first = -1;
ICSState *ics = &icp->ics[src];
@@ -810,7 +811,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
}
}
-void xics_free(XICSState *icp, int irq, int num)
+void xics_spapr_free(XICSState *icp, int irq, int num)
{
int src = xics_find_source(icp, irq);
@@ -1029,7 +1030,7 @@ static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
}
}
-static void xics_realize(DeviceState *dev, Error **errp)
+static void xics_spapr_realize(DeviceState *dev, Error **errp)
{
XICSState *icp = XICS(dev);
Error *error = NULL;
@@ -1068,7 +1069,7 @@ static void xics_realize(DeviceState *dev, Error **errp)
}
}
-static void xics_initfn(Object *obj)
+static void xics_spapr_initfn(Object *obj)
{
XICSState *xics = XICS(obj);
@@ -1077,29 +1078,29 @@ static void xics_initfn(Object *obj)
xics->ics->icp = xics;
}
-static void xics_class_init(ObjectClass *oc, void *data)
+static void xics_spapr_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
- XICSStateClass *xsc = XICS_CLASS(oc);
+ XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
- dc->realize = xics_realize;
+ dc->realize = xics_spapr_realize;
xsc->set_nr_irqs = xics_set_nr_irqs;
xsc->set_nr_servers = xics_set_nr_servers;
}
-static const TypeInfo xics_info = {
- .name = TYPE_XICS,
+static const TypeInfo xics_spapr_info = {
+ .name = TYPE_XICS_SPAPR,
.parent = TYPE_XICS_COMMON,
.instance_size = sizeof(XICSState),
.class_size = sizeof(XICSStateClass),
- .class_init = xics_class_init,
- .instance_init = xics_initfn,
+ .class_init = xics_spapr_class_init,
+ .instance_init = xics_spapr_initfn,
};
static void xics_register_types(void)
{
type_register_static(&xics_common_info);
- type_register_static(&xics_info);
+ type_register_static(&xics_spapr_info);
type_register_static(&ics_info);
type_register_static(&icp_info);
}
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index b17d6a9..90d657e 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -495,8 +495,8 @@ static void xics_kvm_class_init(ObjectClass *oc, void *data)
xsc->set_nr_servers = xics_kvm_set_nr_servers;
}
-static const TypeInfo xics_kvm_info = {
- .name = TYPE_KVM_XICS,
+static const TypeInfo xics_spapr_kvm_info = {
+ .name = TYPE_XICS_SPAPR_KVM,
.parent = TYPE_XICS_COMMON,
.instance_size = sizeof(KVMXICSState),
.class_init = xics_kvm_class_init,
@@ -505,7 +505,7 @@ static const TypeInfo xics_kvm_info = {
static void xics_kvm_register_types(void)
{
- type_register_static(&xics_kvm_info);
+ type_register_static(&xics_spapr_kvm_info);
type_register_static(&ics_kvm_info);
type_register_static(&icp_kvm_info);
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 0b6bb9c..a8d497c 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -122,7 +122,8 @@ static XICSState *xics_system_init(MachineState *machine,
Error *err = NULL;
if (machine_kernel_irqchip_allowed(machine)) {
- icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
+ icp = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
+ &err);
}
if (machine_kernel_irqchip_required(machine) && !icp) {
error_reportf_err(err,
@@ -133,7 +134,7 @@ static XICSState *xics_system_init(MachineState *machine,
}
if (!icp) {
- icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
+ icp = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
}
return icp;
@@ -1781,7 +1782,7 @@ static void ppc_spapr_init(MachineState *machine)
/* Set up Interrupt Controller before we create the VCPUs */
spapr->icp = xics_system_init(machine,
DIV_ROUND_UP(max_cpus * smt, smp_threads),
- XICS_IRQS, &error_fatal);
+ XICS_IRQS_SPAPR, &error_fatal);
if (smc->dr_lmb_enabled) {
spapr_validate_node_memory(machine, &error_fatal);
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index af80992..0585f8a 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -603,7 +603,7 @@ out_no_events:
void spapr_events_init(sPAPRMachineState *spapr)
{
QTAILQ_INIT(&spapr->pending_events);
- spapr->check_exception_irq = xics_alloc(spapr->icp, 0, 0, false,
+ spapr->check_exception_irq = xics_spapr_alloc(spapr->icp, 0, 0, false,
&error_fatal);
spapr->epow_notifier.notify = spapr_powerdown_req;
qemu_register_powerdown_notifier(&spapr->epow_notifier);
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 9f28fb3..451651d 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -322,7 +322,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return;
}
- xics_free(spapr->icp, msi->first_irq, msi->num);
+ xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
if (msi_present(pdev)) {
spapr_msi_setmsg(pdev, 0, false, 0, 0);
}
@@ -360,7 +360,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
/* Allocate MSIs */
- irq = xics_alloc_block(spapr->icp, 0, req_num, false,
+ irq = xics_spapr_alloc_block(spapr->icp, 0, req_num, false,
ret_intr_type == RTAS_TYPE_MSI, &err);
if (err) {
error_reportf_err(err, "Can't allocate MSIs for device %x: ",
@@ -371,7 +371,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
/* Release previous MSIs */
if (msi) {
- xics_free(spapr->icp, msi->first_irq, msi->num);
+ xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
g_hash_table_remove(phb->msi, &config_addr);
}
@@ -1442,7 +1442,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
uint32_t irq;
Error *local_err = NULL;
- irq = xics_alloc_block(spapr->icp, 0, 1, true, false, &local_err);
+ irq = xics_spapr_alloc_block(spapr->icp, 0, 1, true, false, &local_err);
if (local_err) {
error_propagate(errp, local_err);
error_prepend(errp, "can't allocate LSIs: ");
@@ -1801,7 +1801,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb,
_FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
_FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
_FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
- _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS));
+ _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
/* Build the interrupt-map, this must matches what is done
* in pci_spapr_map_irq
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index ae40db8..7ffd23e 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -463,7 +463,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
dev->qdev.id = id;
}
- dev->irq = xics_alloc(spapr->icp, 0, dev->irq, false, &local_err);
+ dev->irq = xics_spapr_alloc(spapr->icp, 0, dev->irq, false, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 9091054..452a978 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -32,20 +32,24 @@
#define TYPE_XICS_COMMON "xics-common"
#define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
-#define TYPE_XICS "xics"
-#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
+/*
+ * Retain xics as the type name to be compatible for migration. Rest all the
+ * functions, class and variables are renamed as xics_spapr.
+ */
+#define TYPE_XICS_SPAPR "xics"
+#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
-#define TYPE_KVM_XICS "xics-kvm"
-#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS)
+#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
+#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
#define XICS_COMMON_CLASS(klass) \
OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
-#define XICS_CLASS(klass) \
- OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS)
+#define XICS_SPAPR_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
#define XICS_COMMON_GET_CLASS(obj) \
OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
-#define XICS_GET_CLASS(obj) \
- OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS)
+#define XICS_SPAPR_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
#define XICS_IPI 0x2
#define XICS_BUID 0x1
@@ -157,14 +161,15 @@ struct ICSIRQState {
uint8_t flags;
};
-#define XICS_IRQS 1024
+#define XICS_IRQS_SPAPR 1024
qemu_irq xics_get_qirq(XICSState *icp, int irq);
void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
-int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp);
-int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
+int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
Error **errp);
-void xics_free(XICSState *icp, int irq, int num);
+int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
+ bool align, Error **errp);
+void xics_spapr_free(XICSState *icp, int irq, int num);
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-24 5:19 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor Nikunj A Dadhania
` (8 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Leave the core ICP/ICS logic in xics.c and move the top level
class wrapper, hypercall and RTAS handlers to xics_spapr.c
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to
xics_spapr.c]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
default-configs/ppc64-softmmu.mak | 1 +
hw/intc/Makefile.objs | 1 +
hw/intc/xics.c | 418 +-----------------------------------
hw/intc/xics_spapr.c | 432 ++++++++++++++++++++++++++++++++++++++
include/hw/ppc/xics.h | 21 ++
5 files changed, 464 insertions(+), 409 deletions(-)
create mode 100644 hw/intc/xics_spapr.c
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index bb71b23..c4be59f 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -49,6 +49,7 @@ CONFIG_ETSEC=y
CONFIG_LIBDECNUMBER=y
# For pSeries
CONFIG_XICS=$(CONFIG_PSERIES)
+CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
# For PReP
CONFIG_MC146818RTC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index c7bbf88..530df2e 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
obj-$(CONFIG_SH4) += sh_intc.o
obj-$(CONFIG_XICS) += xics.o
+obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
obj-$(CONFIG_XICS_KVM) += xics_kvm.o
obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
obj-$(CONFIG_S390_FLIC) += s390_flic.o
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index a715532..6ca391f 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -32,12 +32,11 @@
#include "hw/hw.h"
#include "trace.h"
#include "qemu/timer.h"
-#include "hw/ppc/spapr.h"
#include "hw/ppc/xics.h"
#include "qemu/error-report.h"
#include "qapi/visitor.h"
-static int get_cpu_index_by_dt_id(int cpu_dt_id)
+int get_cpu_index_by_dt_id(int cpu_dt_id)
{
PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
@@ -242,7 +241,7 @@ static void icp_resend(XICSState *icp, int server)
ics_resend(icp->ics);
}
-static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
+void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
{
ICPState *ss = icp->ss + server;
uint8_t old_cppr;
@@ -266,7 +265,7 @@ static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
}
}
-static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
+void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
{
ICPState *ss = icp->ss + server;
@@ -276,7 +275,7 @@ static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
}
}
-static uint32_t icp_accept(ICPState *ss)
+uint32_t icp_accept(ICPState *ss)
{
uint32_t xirr = ss->xirr;
@@ -289,7 +288,7 @@ static uint32_t icp_accept(ICPState *ss)
return xirr;
}
-static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
+void icp_eoi(XICSState *icp, int server, uint32_t xirr)
{
ICPState *ss = icp->ss + server;
@@ -390,12 +389,6 @@ static const TypeInfo icp_info = {
/*
* ICS: Source layer
*/
-static int ics_valid_irq(ICSState *ics, uint32_t nr)
-{
- return (nr >= ics->offset)
- && (nr < (ics->offset + ics->nr_irqs));
-}
-
static void resend_msi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -480,8 +473,8 @@ static void write_xive_lsi(ICSState *ics, int srcno)
resend_lsi(ics, srcno);
}
-static void ics_write_xive(ICSState *ics, int nr, int server,
- uint8_t priority, uint8_t saved_priority)
+void ics_write_xive(ICSState *ics, int nr, int server,
+ uint8_t priority, uint8_t saved_priority)
{
int srcno = nr - ics->offset;
ICSIRQState *irq = ics->irqs + srcno;
@@ -658,7 +651,7 @@ static const TypeInfo ics_info = {
/*
* Exported functions
*/
-static int xics_find_source(XICSState *icp, int irq)
+int xics_find_source(XICSState *icp, int irq)
{
int sources = 1;
int src;
@@ -686,7 +679,7 @@ qemu_irq xics_get_qirq(XICSState *icp, int irq)
return NULL;
}
-static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
+void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
{
assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
@@ -705,402 +698,9 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
ics_set_irq_type(ics, irq - ics->offset, lsi);
}
-#define ICS_IRQ_FREE(ics, srcno) \
- (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
-
-static int ics_find_free_block(ICSState *ics, int num, int alignnum)
-{
- int first, i;
-
- for (first = 0; first < ics->nr_irqs; first += alignnum) {
- if (num > (ics->nr_irqs - first)) {
- return -1;
- }
- for (i = first; i < first + num; ++i) {
- if (!ICS_IRQ_FREE(ics, i)) {
- break;
- }
- }
- if (i == (first + num)) {
- return first;
- }
- }
-
- return -1;
-}
-
-int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
- Error **errp)
-{
- ICSState *ics = &icp->ics[src];
- int irq;
-
- if (irq_hint) {
- assert(src == xics_find_source(icp, irq_hint));
- if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
- error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
- return -1;
- }
- irq = irq_hint;
- } else {
- irq = ics_find_free_block(ics, 1, 1);
- if (irq < 0) {
- error_setg(errp, "can't allocate IRQ: no IRQ left");
- return -1;
- }
- irq += ics->offset;
- }
-
- ics_set_irq_type(ics, irq - ics->offset, lsi);
- trace_xics_alloc(src, irq);
-
- return irq;
-}
-
-/*
- * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
- * If align==true, aligns the first IRQ number to num.
- */
-int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
- bool align, Error **errp)
-{
- int i, first = -1;
- ICSState *ics = &icp->ics[src];
-
- assert(src == 0);
- /*
- * MSIMesage::data is used for storing VIRQ so
- * it has to be aligned to num to support multiple
- * MSI vectors. MSI-X is not affected by this.
- * The hint is used for the first IRQ, the rest should
- * be allocated continuously.
- */
- if (align) {
- assert((num == 1) || (num == 2) || (num == 4) ||
- (num == 8) || (num == 16) || (num == 32));
- first = ics_find_free_block(ics, num, num);
- } else {
- first = ics_find_free_block(ics, num, 1);
- }
- if (first < 0) {
- error_setg(errp, "can't find a free %d-IRQ block", num);
- return -1;
- }
-
- if (first >= 0) {
- for (i = first; i < first + num; ++i) {
- ics_set_irq_type(ics, i, lsi);
- }
- }
- first += ics->offset;
-
- trace_xics_alloc_block(src, first, num, lsi, align);
-
- return first;
-}
-
-static void ics_free(ICSState *ics, int srcno, int num)
-{
- int i;
-
- for (i = srcno; i < srcno + num; ++i) {
- if (ICS_IRQ_FREE(ics, i)) {
- trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
- }
- memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
- }
-}
-
-void xics_spapr_free(XICSState *icp, int irq, int num)
-{
- int src = xics_find_source(icp, irq);
-
- if (src >= 0) {
- ICSState *ics = &icp->ics[src];
-
- /* FIXME: implement multiple sources */
- assert(src == 0);
-
- trace_xics_ics_free(ics - icp->ics, irq, num);
- ics_free(ics, irq - ics->offset, num);
- }
-}
-
-/*
- * Guest interfaces
- */
-
-static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUState *cs = CPU(cpu);
- target_ulong cppr = args[0];
-
- icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
- return H_SUCCESS;
-}
-
-static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- target_ulong server = get_cpu_index_by_dt_id(args[0]);
- target_ulong mfrr = args[1];
-
- if (server >= spapr->icp->nr_servers) {
- return H_PARAMETER;
- }
-
- icp_set_mfrr(spapr->icp, server, mfrr);
- return H_SUCCESS;
-}
-
-static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUState *cs = CPU(cpu);
- uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
-
- args[0] = xirr;
- return H_SUCCESS;
-}
-
-static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUState *cs = CPU(cpu);
- ICPState *ss = &spapr->icp->ss[cs->cpu_index];
- uint32_t xirr = icp_accept(ss);
-
- args[0] = xirr;
- args[1] = cpu_get_host_ticks();
- return H_SUCCESS;
-}
-
-static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUState *cs = CPU(cpu);
- target_ulong xirr = args[0];
-
- icp_eoi(spapr->icp, cs->cpu_index, xirr);
- return H_SUCCESS;
-}
-
-static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- target_ulong opcode, target_ulong *args)
-{
- CPUState *cs = CPU(cpu);
- ICPState *ss = &spapr->icp->ss[cs->cpu_index];
-
- args[0] = ss->xirr;
- args[1] = ss->mfrr;
-
- return H_SUCCESS;
-}
-
-static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- uint32_t token,
- uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets)
-{
- ICSState *ics = spapr->icp->ics;
- uint32_t nr, server, priority;
-
- if ((nargs != 3) || (nret != 1)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- nr = rtas_ld(args, 0);
- server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
- priority = rtas_ld(args, 2);
-
- if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
- || (priority > 0xff)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- ics_write_xive(ics, nr, server, priority, priority);
-
- rtas_st(rets, 0, RTAS_OUT_SUCCESS);
-}
-
-static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- uint32_t token,
- uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets)
-{
- ICSState *ics = spapr->icp->ics;
- uint32_t nr;
-
- if ((nargs != 1) || (nret != 3)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- nr = rtas_ld(args, 0);
-
- if (!ics_valid_irq(ics, nr)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- rtas_st(rets, 0, RTAS_OUT_SUCCESS);
- rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
- rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
-}
-
-static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- uint32_t token,
- uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets)
-{
- ICSState *ics = spapr->icp->ics;
- uint32_t nr;
-
- if ((nargs != 1) || (nret != 1)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- nr = rtas_ld(args, 0);
-
- if (!ics_valid_irq(ics, nr)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
- ics->irqs[nr - ics->offset].priority);
-
- rtas_st(rets, 0, RTAS_OUT_SUCCESS);
-}
-
-static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
- uint32_t token,
- uint32_t nargs, target_ulong args,
- uint32_t nret, target_ulong rets)
-{
- ICSState *ics = spapr->icp->ics;
- uint32_t nr;
-
- if ((nargs != 1) || (nret != 1)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- nr = rtas_ld(args, 0);
-
- if (!ics_valid_irq(ics, nr)) {
- rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
- return;
- }
-
- ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
- ics->irqs[nr - ics->offset].saved_priority,
- ics->irqs[nr - ics->offset].saved_priority);
-
- rtas_st(rets, 0, RTAS_OUT_SUCCESS);
-}
-
-/*
- * XICS
- */
-
-static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
-{
- icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
-}
-
-static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
- Error **errp)
-{
- int i;
-
- icp->nr_servers = nr_servers;
-
- icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
- for (i = 0; i < icp->nr_servers; i++) {
- char buffer[32];
- object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
- snprintf(buffer, sizeof(buffer), "icp[%d]", i);
- object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
- errp);
- }
-}
-
-static void xics_spapr_realize(DeviceState *dev, Error **errp)
-{
- XICSState *icp = XICS(dev);
- Error *error = NULL;
- int i;
-
- if (!icp->nr_servers) {
- error_setg(errp, "Number of servers needs to be greater 0");
- return;
- }
-
- /* Registration of global state belongs into realize */
- spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
- spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
- spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
- spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
-
- spapr_register_hypercall(H_CPPR, h_cppr);
- spapr_register_hypercall(H_IPI, h_ipi);
- spapr_register_hypercall(H_XIRR, h_xirr);
- spapr_register_hypercall(H_XIRR_X, h_xirr_x);
- spapr_register_hypercall(H_EOI, h_eoi);
- spapr_register_hypercall(H_IPOLL, h_ipoll);
-
- object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
- if (error) {
- error_propagate(errp, error);
- return;
- }
-
- for (i = 0; i < icp->nr_servers; i++) {
- object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
- if (error) {
- error_propagate(errp, error);
- return;
- }
- }
-}
-
-static void xics_spapr_initfn(Object *obj)
-{
- XICSState *xics = XICS(obj);
-
- xics->ics = ICS(object_new(TYPE_ICS));
- object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->icp = xics;
-}
-
-static void xics_spapr_class_init(ObjectClass *oc, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(oc);
- XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
-
- dc->realize = xics_spapr_realize;
- xsc->set_nr_irqs = xics_set_nr_irqs;
- xsc->set_nr_servers = xics_set_nr_servers;
-}
-
-static const TypeInfo xics_spapr_info = {
- .name = TYPE_XICS_SPAPR,
- .parent = TYPE_XICS_COMMON,
- .instance_size = sizeof(XICSState),
- .class_size = sizeof(XICSStateClass),
- .class_init = xics_spapr_class_init,
- .instance_init = xics_spapr_initfn,
-};
-
static void xics_register_types(void)
{
type_register_static(&xics_common_info);
- type_register_static(&xics_spapr_info);
type_register_static(&ics_info);
type_register_static(&icp_info);
}
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
new file mode 100644
index 0000000..48d458a
--- /dev/null
+++ b/hw/intc/xics_spapr.c
@@ -0,0 +1,432 @@
+/*
+ * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
+ *
+ * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
+ *
+ * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "cpu.h"
+#include "hw/hw.h"
+#include "trace.h"
+#include "qemu/timer.h"
+#include "hw/ppc/spapr.h"
+#include "hw/ppc/xics.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
+
+/*
+ * Guest interfaces
+ */
+
+static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUState *cs = CPU(cpu);
+ target_ulong cppr = args[0];
+
+ icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
+ return H_SUCCESS;
+}
+
+static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ target_ulong server = get_cpu_index_by_dt_id(args[0]);
+ target_ulong mfrr = args[1];
+
+ if (server >= spapr->icp->nr_servers) {
+ return H_PARAMETER;
+ }
+
+ icp_set_mfrr(spapr->icp, server, mfrr);
+ return H_SUCCESS;
+}
+
+static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUState *cs = CPU(cpu);
+ uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
+
+ args[0] = xirr;
+ return H_SUCCESS;
+}
+
+static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUState *cs = CPU(cpu);
+ ICPState *ss = &spapr->icp->ss[cs->cpu_index];
+ uint32_t xirr = icp_accept(ss);
+
+ args[0] = xirr;
+ args[1] = cpu_get_host_ticks();
+ return H_SUCCESS;
+}
+
+static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUState *cs = CPU(cpu);
+ target_ulong xirr = args[0];
+
+ icp_eoi(spapr->icp, cs->cpu_index, xirr);
+ return H_SUCCESS;
+}
+
+static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ target_ulong opcode, target_ulong *args)
+{
+ CPUState *cs = CPU(cpu);
+ ICPState *ss = &spapr->icp->ss[cs->cpu_index];
+
+ args[0] = ss->xirr;
+ args[1] = ss->mfrr;
+
+ return H_SUCCESS;
+}
+
+static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ uint32_t token,
+ uint32_t nargs, target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ ICSState *ics = spapr->icp->ics;
+ uint32_t nr, server, priority;
+
+ if ((nargs != 3) || (nret != 1)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ nr = rtas_ld(args, 0);
+ server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
+ priority = rtas_ld(args, 2);
+
+ if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
+ || (priority > 0xff)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ ics_write_xive(ics, nr, server, priority, priority);
+
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+}
+
+static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ uint32_t token,
+ uint32_t nargs, target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ ICSState *ics = spapr->icp->ics;
+ uint32_t nr;
+
+ if ((nargs != 1) || (nret != 3)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ nr = rtas_ld(args, 0);
+
+ if (!ics_valid_irq(ics, nr)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+ rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
+ rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
+}
+
+static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ uint32_t token,
+ uint32_t nargs, target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ ICSState *ics = spapr->icp->ics;
+ uint32_t nr;
+
+ if ((nargs != 1) || (nret != 1)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ nr = rtas_ld(args, 0);
+
+ if (!ics_valid_irq(ics, nr)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
+ ics->irqs[nr - ics->offset].priority);
+
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+}
+
+static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
+ uint32_t token,
+ uint32_t nargs, target_ulong args,
+ uint32_t nret, target_ulong rets)
+{
+ ICSState *ics = spapr->icp->ics;
+ uint32_t nr;
+
+ if ((nargs != 1) || (nret != 1)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ nr = rtas_ld(args, 0);
+
+ if (!ics_valid_irq(ics, nr)) {
+ rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
+ return;
+ }
+
+ ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
+ ics->irqs[nr - ics->offset].saved_priority,
+ ics->irqs[nr - ics->offset].saved_priority);
+
+ rtas_st(rets, 0, RTAS_OUT_SUCCESS);
+}
+
+static void xics_spapr_set_nr_irqs(XICSState *icp, uint32_t nr_irqs,
+ Error **errp)
+{
+ icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
+}
+
+static void xics_spapr_set_nr_servers(XICSState *icp, uint32_t nr_servers,
+ Error **errp)
+{
+ int i;
+
+ icp->nr_servers = nr_servers;
+
+ icp->ss = g_malloc0(icp->nr_servers * sizeof(ICPState));
+ for (i = 0; i < icp->nr_servers; i++) {
+ char buffer[32];
+ object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
+ snprintf(buffer, sizeof(buffer), "icp[%d]", i);
+ object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
+ errp);
+ }
+}
+
+static void xics_spapr_realize(DeviceState *dev, Error **errp)
+{
+ XICSState *icp = XICS(dev);
+ Error *error = NULL;
+ int i;
+
+ if (!icp->nr_servers) {
+ error_setg(errp, "Number of servers needs to be greater 0");
+ return;
+ }
+
+ /* Registration of global state belongs into realize */
+ spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
+ spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
+ spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
+ spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
+
+ spapr_register_hypercall(H_CPPR, h_cppr);
+ spapr_register_hypercall(H_IPI, h_ipi);
+ spapr_register_hypercall(H_XIRR, h_xirr);
+ spapr_register_hypercall(H_XIRR_X, h_xirr_x);
+ spapr_register_hypercall(H_EOI, h_eoi);
+ spapr_register_hypercall(H_IPOLL, h_ipoll);
+
+ object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+
+ for (i = 0; i < icp->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ }
+}
+
+static void xics_spapr_initfn(Object *obj)
+{
+ XICSState *xics = XICS(obj);
+
+ xics->ics = ICS(object_new(TYPE_ICS));
+ object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
+ xics->ics->icp = xics;
+}
+
+static void xics_spapr_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
+
+ dc->realize = xics_spapr_realize;
+ xsc->set_nr_irqs = xics_spapr_set_nr_irqs;
+ xsc->set_nr_servers = xics_spapr_set_nr_servers;
+}
+
+static const TypeInfo xics_spapr_info = {
+ .name = TYPE_XICS_SPAPR,
+ .parent = TYPE_XICS_COMMON,
+ .instance_size = sizeof(XICSState),
+ .class_size = sizeof(XICSStateClass),
+ .class_init = xics_spapr_class_init,
+ .instance_init = xics_spapr_initfn,
+};
+
+#define ICS_IRQ_FREE(ics, srcno) \
+ (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
+
+static int ics_find_free_block(ICSState *ics, int num, int alignnum)
+{
+ int first, i;
+
+ for (first = 0; first < ics->nr_irqs; first += alignnum) {
+ if (num > (ics->nr_irqs - first)) {
+ return -1;
+ }
+ for (i = first; i < first + num; ++i) {
+ if (!ICS_IRQ_FREE(ics, i)) {
+ break;
+ }
+ }
+ if (i == (first + num)) {
+ return first;
+ }
+ }
+
+ return -1;
+}
+
+int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
+ Error **errp)
+{
+ ICSState *ics = &icp->ics[src];
+ int irq;
+
+ if (irq_hint) {
+ assert(src == xics_find_source(icp, irq_hint));
+ if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
+ error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
+ return -1;
+ }
+ irq = irq_hint;
+ } else {
+ irq = ics_find_free_block(ics, 1, 1);
+ if (irq < 0) {
+ error_setg(errp, "can't allocate IRQ: no IRQ left");
+ return -1;
+ }
+ irq += ics->offset;
+ }
+
+ ics_set_irq_type(ics, irq - ics->offset, lsi);
+ trace_xics_alloc(src, irq);
+
+ return irq;
+}
+
+/*
+ * Allocate block of consecutive IRQs, and return the number of the first IRQ in
+ * the block. If align==true, aligns the first IRQ number to num.
+ */
+int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
+ bool align, Error **errp)
+{
+ int i, first = -1;
+ ICSState *ics = &icp->ics[src];
+
+ assert(src == 0);
+ /*
+ * MSIMesage::data is used for storing VIRQ so
+ * it has to be aligned to num to support multiple
+ * MSI vectors. MSI-X is not affected by this.
+ * The hint is used for the first IRQ, the rest should
+ * be allocated continuously.
+ */
+ if (align) {
+ assert((num == 1) || (num == 2) || (num == 4) ||
+ (num == 8) || (num == 16) || (num == 32));
+ first = ics_find_free_block(ics, num, num);
+ } else {
+ first = ics_find_free_block(ics, num, 1);
+ }
+ if (first < 0) {
+ error_setg(errp, "can't find a free %d-IRQ block", num);
+ return -1;
+ }
+
+ if (first >= 0) {
+ for (i = first; i < first + num; ++i) {
+ ics_set_irq_type(ics, i, lsi);
+ }
+ }
+ first += ics->offset;
+
+ trace_xics_alloc_block(src, first, num, lsi, align);
+
+ return first;
+}
+
+static void ics_free(ICSState *ics, int srcno, int num)
+{
+ int i;
+
+ for (i = srcno; i < srcno + num; ++i) {
+ if (ICS_IRQ_FREE(ics, i)) {
+ trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
+ }
+ memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
+ }
+}
+
+void xics_spapr_free(XICSState *icp, int irq, int num)
+{
+ int src = xics_find_source(icp, irq);
+
+ if (src >= 0) {
+ ICSState *ics = &icp->ics[src];
+
+ /* FIXME: implement multiple sources */
+ assert(src == 0);
+
+ trace_xics_ics_free(ics - icp->ics, irq, num);
+ ics_free(ics, irq - ics->offset, num);
+ }
+}
+
+static void xics_spapr_register_types(void)
+{
+ type_register_static(&xics_spapr_info);
+}
+
+type_init(xics_spapr_register_types)
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 452a978..76b45ef 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -145,6 +145,12 @@ struct ICSState {
XICSState *icp;
};
+static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
+{
+ return (nr >= ics->offset)
+ && (nr < (ics->offset + ics->nr_irqs));
+}
+
struct ICSIRQState {
uint32_t server;
uint8_t priority;
@@ -174,4 +180,19 @@ void xics_spapr_free(XICSState *icp, int irq, int num);
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
+/* Internal XICS interfaces */
+int get_cpu_index_by_dt_id(int cpu_dt_id);
+
+void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
+void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
+uint32_t icp_accept(ICPState *ss);
+void icp_eoi(XICSState *icp, int server, uint32_t xirr);
+
+void ics_write_xive(ICSState *ics, int nr, int server,
+ uint8_t priority, uint8_t saved_priority);
+
+void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
+
+int xics_find_source(XICSState *icp, int irq);
+
#endif /* __XICS_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-24 5:21 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type() Nikunj A Dadhania
` (7 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
None of the other presenter functions directly mucks with the
internal state, so don't do it there either.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 8 ++++++++
hw/intc/xics_spapr.c | 7 ++++---
include/hw/ppc/xics.h | 1 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 6ca391f..40969ee 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -288,6 +288,14 @@ uint32_t icp_accept(ICPState *ss)
return xirr;
}
+uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
+{
+ if (mfrr) {
+ *mfrr = ss->mfrr;
+ }
+ return ss->xirr;
+}
+
void icp_eoi(XICSState *icp, int server, uint32_t xirr)
{
ICPState *ss = icp->ss + server;
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 48d458a..4d5adda 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -99,10 +99,11 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
- ICPState *ss = &spapr->icp->ss[cs->cpu_index];
+ uint32_t mfrr;
+ uint32_t xirr = icp_ipoll(spapr->icp->ss + cs->cpu_index, &mfrr);
- args[0] = ss->xirr;
- args[1] = ss->mfrr;
+ args[0] = xirr;
+ args[1] = mfrr;
return H_SUCCESS;
}
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 76b45ef..32ea706 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -186,6 +186,7 @@ int get_cpu_index_by_dt_id(int cpu_dt_id);
void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
uint32_t icp_accept(ICPState *ss);
+uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
void icp_eoi(XICSState *icp, int server, uint32_t xirr);
void ics_write_xive(ICSState *ics, int nr, int server,
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type()
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (2 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-24 5:45 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places Nikunj A Dadhania
` (6 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 11 -----------
include/hw/ppc/xics.h | 1 -
2 files changed, 12 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 40969ee..4f15a2d 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -695,17 +695,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
}
-void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
-{
- int src = xics_find_source(icp, irq);
- ICSState *ics;
-
- assert(src >= 0);
-
- ics = &icp->ics[src];
- ics_set_irq_type(ics, irq - ics->offset, lsi);
-}
-
static void xics_register_types(void)
{
type_register_static(&xics_common_info);
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 32ea706..2a9b91d 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -170,7 +170,6 @@ struct ICSIRQState {
#define XICS_IRQS_SPAPR 1024
qemu_irq xics_get_qirq(XICSState *icp, int irq);
-void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
Error **errp);
int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (3 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type() Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 3:43 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list Nikunj A Dadhania
` (5 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The "ICP" is a different object than the "XICS". For historical reasons,
we have a number of places where we name a variable "icp" while it contains
a XICSState pointer. There *is* an ICPState structure too so this makes
the code really confusing.
This is a mechanical replacement of all those instances to use the name
"xics" instead. There should be no functional change.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[spapr_cpu_init has been moved to spapr_cpu_core.c, change there]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 120 ++++++++++++++++++++++----------------------
hw/intc/xics_kvm.c | 57 +++++++++++----------
hw/intc/xics_spapr.c | 73 ++++++++++++++-------------
hw/ppc/spapr.c | 20 ++++----
hw/ppc/spapr_cpu_core.c | 4 +-
hw/ppc/spapr_events.c | 8 +--
hw/ppc/spapr_pci.c | 11 ++--
hw/ppc/spapr_vio.c | 2 +-
include/hw/pci-host/spapr.h | 2 +-
include/hw/ppc/spapr.h | 2 +-
include/hw/ppc/spapr_vio.h | 2 +-
include/hw/ppc/xics.h | 2 +-
12 files changed, 154 insertions(+), 149 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 4f15a2d..38e51fc 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -47,31 +47,31 @@ int get_cpu_index_by_dt_id(int cpu_dt_id)
return -1;
}
-void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu)
+void xics_cpu_destroy(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
- ICPState *ss = &icp->ss[cs->cpu_index];
+ ICPState *ss = &xics->ss[cs->cpu_index];
- assert(cs->cpu_index < icp->nr_servers);
+ assert(cs->cpu_index < xics->nr_servers);
assert(cs == ss->cs);
ss->output = NULL;
ss->cs = NULL;
}
-void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
+void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- ICPState *ss = &icp->ss[cs->cpu_index];
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ ICPState *ss = &xics->ss[cs->cpu_index];
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
- assert(cs->cpu_index < icp->nr_servers);
+ assert(cs->cpu_index < xics->nr_servers);
ss->cs = cs;
if (info->cpu_setup) {
- info->cpu_setup(icp, cpu);
+ info->cpu_setup(xics, cpu);
}
switch (PPC_INPUT(env)) {
@@ -95,21 +95,21 @@ void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
*/
static void xics_common_reset(DeviceState *d)
{
- XICSState *icp = XICS_COMMON(d);
+ XICSState *xics = XICS_COMMON(d);
int i;
- for (i = 0; i < icp->nr_servers; i++) {
- device_reset(DEVICE(&icp->ss[i]));
+ for (i = 0; i < xics->nr_servers; i++) {
+ device_reset(DEVICE(&xics->ss[i]));
}
- device_reset(DEVICE(icp->ics));
+ device_reset(DEVICE(xics->ics));
}
static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- int64_t value = icp->nr_irqs;
+ XICSState *xics = XICS_COMMON(obj);
+ int64_t value = xics->nr_irqs;
visit_type_int(v, name, &value, errp);
}
@@ -117,8 +117,8 @@ static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ XICSState *xics = XICS_COMMON(obj);
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
Error *error = NULL;
int64_t value;
@@ -127,23 +127,23 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
error_propagate(errp, error);
return;
}
- if (icp->nr_irqs) {
+ if (xics->nr_irqs) {
error_setg(errp, "Number of interrupts is already set to %u",
- icp->nr_irqs);
+ xics->nr_irqs);
return;
}
assert(info->set_nr_irqs);
- assert(icp->ics);
- info->set_nr_irqs(icp, value, errp);
+ assert(xics->ics);
+ info->set_nr_irqs(xics, value, errp);
}
static void xics_prop_get_nr_servers(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- int64_t value = icp->nr_servers;
+ XICSState *xics = XICS_COMMON(obj);
+ int64_t value = xics->nr_servers;
visit_type_int(v, name, &value, errp);
}
@@ -152,8 +152,8 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
const char *name, void *opaque,
Error **errp)
{
- XICSState *icp = XICS_COMMON(obj);
- XICSStateClass *info = XICS_COMMON_GET_CLASS(icp);
+ XICSState *xics = XICS_COMMON(obj);
+ XICSStateClass *info = XICS_COMMON_GET_CLASS(xics);
Error *error = NULL;
int64_t value;
@@ -162,14 +162,14 @@ static void xics_prop_set_nr_servers(Object *obj, Visitor *v,
error_propagate(errp, error);
return;
}
- if (icp->nr_servers) {
+ if (xics->nr_servers) {
error_setg(errp, "Number of servers is already set to %u",
- icp->nr_servers);
+ xics->nr_servers);
return;
}
assert(info->set_nr_servers);
- info->set_nr_servers(icp, value, errp);
+ info->set_nr_servers(xics, value, errp);
}
static void xics_common_initfn(Object *obj)
@@ -212,9 +212,9 @@ static void ics_reject(ICSState *ics, int nr);
static void ics_resend(ICSState *ics);
static void ics_eoi(ICSState *ics, int nr);
-static void icp_check_ipi(XICSState *icp, int server)
+static void icp_check_ipi(XICSState *xics, int server)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
return;
@@ -223,7 +223,7 @@ static void icp_check_ipi(XICSState *icp, int server)
trace_xics_icp_check_ipi(server, ss->mfrr);
if (XISR(ss)) {
- ics_reject(icp->ics, XISR(ss));
+ ics_reject(xics->ics, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
@@ -231,19 +231,19 @@ static void icp_check_ipi(XICSState *icp, int server)
qemu_irq_raise(ss->output);
}
-static void icp_resend(XICSState *icp, int server)
+static void icp_resend(XICSState *xics, int server)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
if (ss->mfrr < CPPR(ss)) {
- icp_check_ipi(icp, server);
+ icp_check_ipi(xics, server);
}
- ics_resend(icp->ics);
+ ics_resend(xics->ics);
}
-void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
+void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
uint8_t old_cppr;
uint32_t old_xisr;
@@ -256,22 +256,22 @@ void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
ss->xirr &= ~XISR_MASK; /* Clear XISR */
ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
- ics_reject(icp->ics, old_xisr);
+ ics_reject(xics->ics, old_xisr);
}
} else {
if (!XISR(ss)) {
- icp_resend(icp, server);
+ icp_resend(xics, server);
}
}
}
-void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
+void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
ss->mfrr = mfrr;
if (mfrr < CPPR(ss)) {
- icp_check_ipi(icp, server);
+ icp_check_ipi(xics, server);
}
}
@@ -296,31 +296,31 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
return ss->xirr;
}
-void icp_eoi(XICSState *icp, int server, uint32_t xirr)
+void icp_eoi(XICSState *xics, int server, uint32_t xirr)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
/* Send EOI -> ICS */
ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
trace_xics_icp_eoi(server, xirr, ss->xirr);
- ics_eoi(icp->ics, xirr & XISR_MASK);
+ ics_eoi(xics->ics, xirr & XISR_MASK);
if (!XISR(ss)) {
- icp_resend(icp, server);
+ icp_resend(xics, server);
}
}
-static void icp_irq(XICSState *icp, int server, int nr, uint8_t priority)
+static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)
{
- ICPState *ss = icp->ss + server;
+ ICPState *ss = xics->ss + server;
trace_xics_icp_irq(server, nr, priority);
if ((priority >= CPPR(ss))
|| (XISR(ss) && (ss->pending_priority <= priority))) {
- ics_reject(icp->ics, nr);
+ ics_reject(xics->ics, nr);
} else {
if (XISR(ss)) {
- ics_reject(icp->ics, XISR(ss));
+ ics_reject(xics->ics, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
ss->pending_priority = priority;
@@ -405,7 +405,7 @@ static void resend_msi(ICSState *ics, int srcno)
if (irq->status & XICS_STATUS_REJECTED) {
irq->status &= ~XICS_STATUS_REJECTED;
if (irq->priority != 0xff) {
- icp_irq(ics->icp, irq->server, srcno + ics->offset,
+ icp_irq(ics->xics, irq->server, srcno + ics->offset,
irq->priority);
}
}
@@ -419,7 +419,7 @@ static void resend_lsi(ICSState *ics, int srcno)
&& (irq->status & XICS_STATUS_ASSERTED)
&& !(irq->status & XICS_STATUS_SENT)) {
irq->status |= XICS_STATUS_SENT;
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
}
@@ -434,7 +434,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
irq->status |= XICS_STATUS_MASKED_PENDING;
trace_xics_masked_pending();
} else {
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
}
}
@@ -473,7 +473,7 @@ static void write_xive_msi(ICSState *ics, int srcno)
}
irq->status &= ~XICS_STATUS_MASKED_PENDING;
- icp_irq(ics->icp, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
}
static void write_xive_lsi(ICSState *ics, int srcno)
@@ -558,8 +558,8 @@ static int ics_post_load(ICSState *ics, int version_id)
{
int i;
- for (i = 0; i < ics->icp->nr_servers; i++) {
- icp_resend(ics->icp, i);
+ for (i = 0; i < ics->xics->nr_servers; i++) {
+ icp_resend(ics->xics, i);
}
return 0;
@@ -659,14 +659,14 @@ static const TypeInfo ics_info = {
/*
* Exported functions
*/
-int xics_find_source(XICSState *icp, int irq)
+int xics_find_source(XICSState *xics, int irq)
{
int sources = 1;
int src;
/* FIXME: implement multiple sources */
for (src = 0; src < sources; ++src) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
if (ics_valid_irq(ics, irq)) {
return src;
}
@@ -675,12 +675,12 @@ int xics_find_source(XICSState *icp, int irq)
return -1;
}
-qemu_irq xics_get_qirq(XICSState *icp, int irq)
+qemu_irq xics_get_qirq(XICSState *xics, int irq)
{
- int src = xics_find_source(icp, irq);
+ int src = xics_find_source(xics, irq);
if (src >= 0) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
return ics->qirqs[irq - ics->offset];
}
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 90d657e..64d2256 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -145,7 +145,7 @@ static const TypeInfo icp_kvm_info = {
*/
static void ics_get_kvm_state(ICSState *ics)
{
- KVMXICSState *icpkvm = KVM_XICS(ics->icp);
+ KVMXICSState *xicskvm = KVM_XICS(ics->xics);
uint64_t state;
struct kvm_device_attr attr = {
.flags = 0,
@@ -160,7 +160,7 @@ static void ics_get_kvm_state(ICSState *ics)
attr.attr = i + ics->offset;
- ret = ioctl(icpkvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
+ ret = ioctl(xicskvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
if (ret != 0) {
error_report("Unable to retrieve KVM interrupt controller state"
" for IRQ %d: %s", i + ics->offset, strerror(errno));
@@ -204,7 +204,7 @@ static void ics_get_kvm_state(ICSState *ics)
static int ics_set_kvm_state(ICSState *ics, int version_id)
{
- KVMXICSState *icpkvm = KVM_XICS(ics->icp);
+ KVMXICSState *xicskvm = KVM_XICS(ics->xics);
uint64_t state;
struct kvm_device_attr attr = {
.flags = 0,
@@ -238,7 +238,7 @@ static int ics_set_kvm_state(ICSState *ics, int version_id)
}
}
- ret = ioctl(icpkvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
+ ret = ioctl(xicskvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
if (ret != 0) {
error_report("Unable to restore KVM interrupt controller state"
" for IRQs %d: %s", i + ics->offset, strerror(errno));
@@ -324,17 +324,17 @@ static const TypeInfo ics_kvm_info = {
/*
* XICS-KVM
*/
-static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
+static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
{
CPUState *cs;
ICPState *ss;
- KVMXICSState *icpkvm = KVM_XICS(icp);
+ KVMXICSState *xicskvm = KVM_XICS(xics);
cs = CPU(cpu);
- ss = &icp->ss[cs->cpu_index];
+ ss = &xics->ss[cs->cpu_index];
- assert(cs->cpu_index < icp->nr_servers);
- if (icpkvm->kernel_xics_fd == -1) {
+ assert(cs->cpu_index < xics->nr_servers);
+ if (xicskvm->kernel_xics_fd == -1) {
abort();
}
@@ -347,11 +347,12 @@ static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
return;
}
- if (icpkvm->kernel_xics_fd != -1) {
+ if (xicskvm->kernel_xics_fd != -1) {
int ret;
ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0,
- icpkvm->kernel_xics_fd, kvm_arch_vcpu_id(cs));
+ xicskvm->kernel_xics_fd,
+ kvm_arch_vcpu_id(cs));
if (ret < 0) {
error_report("Unable to connect CPU%ld to kernel XICS: %s",
kvm_arch_vcpu_id(cs), strerror(errno));
@@ -361,24 +362,25 @@ static void xics_kvm_cpu_setup(XICSState *icp, PowerPCCPU *cpu)
}
}
-static void xics_kvm_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
+static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
+ Error **errp)
{
- icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
+ xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
}
-static void xics_kvm_set_nr_servers(XICSState *icp, uint32_t nr_servers,
+static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
Error **errp)
{
int i;
- icp->nr_servers = nr_servers;
+ xics->nr_servers = nr_servers;
- icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
- for (i = 0; i < icp->nr_servers; i++) {
+ xics->ss = g_malloc0(xics->nr_servers * sizeof(ICPState));
+ for (i = 0; i < xics->nr_servers; i++) {
char buffer[32];
- object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_KVM_ICP);
+ object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_KVM_ICP);
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
- object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
+ object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
errp);
}
}
@@ -394,8 +396,8 @@ static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static void xics_kvm_realize(DeviceState *dev, Error **errp)
{
- KVMXICSState *icpkvm = KVM_XICS(dev);
- XICSState *icp = XICS_COMMON(dev);
+ KVMXICSState *xicskvm = KVM_XICS(dev);
+ XICSState *xics = XICS_COMMON(dev);
int i, rc;
Error *error = NULL;
struct kvm_create_device xics_create_device = {
@@ -445,17 +447,18 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
goto fail;
}
- icpkvm->kernel_xics_fd = xics_create_device.fd;
+ xicskvm->kernel_xics_fd = xics_create_device.fd;
- object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
+ object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
if (error) {
error_propagate(errp, error);
goto fail;
}
- assert(icp->nr_servers);
- for (i = 0; i < icp->nr_servers; i++) {
- object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
+ assert(xics->nr_servers);
+ for (i = 0; i < xics->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
+ &error);
if (error) {
error_propagate(errp, error);
goto fail;
@@ -481,7 +484,7 @@ static void xics_kvm_initfn(Object *obj)
xics->ics = ICS(object_new(TYPE_KVM_ICS));
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->icp = xics;
+ xics->ics->xics = xics;
}
static void xics_kvm_class_init(ObjectClass *oc, void *data)
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 4d5adda..eda15a6 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -45,7 +45,7 @@ static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUState *cs = CPU(cpu);
target_ulong cppr = args[0];
- icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
+ icp_set_cppr(spapr->xics, cs->cpu_index, cppr);
return H_SUCCESS;
}
@@ -55,11 +55,11 @@ static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong server = get_cpu_index_by_dt_id(args[0]);
target_ulong mfrr = args[1];
- if (server >= spapr->icp->nr_servers) {
+ if (server >= spapr->xics->nr_servers) {
return H_PARAMETER;
}
- icp_set_mfrr(spapr->icp, server, mfrr);
+ icp_set_mfrr(spapr->xics, server, mfrr);
return H_SUCCESS;
}
@@ -67,7 +67,7 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
- uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
+ uint32_t xirr = icp_accept(spapr->xics->ss + cs->cpu_index);
args[0] = xirr;
return H_SUCCESS;
@@ -77,7 +77,7 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
target_ulong opcode, target_ulong *args)
{
CPUState *cs = CPU(cpu);
- ICPState *ss = &spapr->icp->ss[cs->cpu_index];
+ ICPState *ss = &spapr->xics->ss[cs->cpu_index];
uint32_t xirr = icp_accept(ss);
args[0] = xirr;
@@ -91,7 +91,7 @@ static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
CPUState *cs = CPU(cpu);
target_ulong xirr = args[0];
- icp_eoi(spapr->icp, cs->cpu_index, xirr);
+ icp_eoi(spapr->xics, cs->cpu_index, xirr);
return H_SUCCESS;
}
@@ -100,7 +100,7 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
{
CPUState *cs = CPU(cpu);
uint32_t mfrr;
- uint32_t xirr = icp_ipoll(spapr->icp->ss + cs->cpu_index, &mfrr);
+ uint32_t xirr = icp_ipoll(spapr->xics->ss + cs->cpu_index, &mfrr);
args[0] = xirr;
args[1] = mfrr;
@@ -113,7 +113,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr, server, priority;
if ((nargs != 3) || (nret != 1)) {
@@ -125,7 +125,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
priority = rtas_ld(args, 2);
- if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
+ if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
|| (priority > 0xff)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
@@ -141,7 +141,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 3)) {
@@ -166,7 +166,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 1)) {
@@ -192,7 +192,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->icp->ics;
+ ICSState *ics = spapr->xics->ics;
uint32_t nr;
if ((nargs != 1) || (nret != 1)) {
@@ -214,36 +214,36 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
-static void xics_spapr_set_nr_irqs(XICSState *icp, uint32_t nr_irqs,
+static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
Error **errp)
{
- icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
+ xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
}
-static void xics_spapr_set_nr_servers(XICSState *icp, uint32_t nr_servers,
+static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
Error **errp)
{
int i;
- icp->nr_servers = nr_servers;
+ xics->nr_servers = nr_servers;
- icp->ss = g_malloc0(icp->nr_servers * sizeof(ICPState));
- for (i = 0; i < icp->nr_servers; i++) {
+ xics->ss = g_malloc0(xics->nr_servers * sizeof(ICPState));
+ for (i = 0; i < xics->nr_servers; i++) {
char buffer[32];
- object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
+ object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_ICP);
snprintf(buffer, sizeof(buffer), "icp[%d]", i);
- object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
+ object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss[i]),
errp);
}
}
static void xics_spapr_realize(DeviceState *dev, Error **errp)
{
- XICSState *icp = XICS(dev);
+ XICSState *xics = XICS(dev);
Error *error = NULL;
int i;
- if (!icp->nr_servers) {
+ if (!xics->nr_servers) {
error_setg(errp, "Number of servers needs to be greater 0");
return;
}
@@ -261,14 +261,15 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
spapr_register_hypercall(H_EOI, h_eoi);
spapr_register_hypercall(H_IPOLL, h_ipoll);
- object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
+ object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
if (error) {
error_propagate(errp, error);
return;
}
- for (i = 0; i < icp->nr_servers; i++) {
- object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
+ for (i = 0; i < xics->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
+ &error);
if (error) {
error_propagate(errp, error);
return;
@@ -282,7 +283,7 @@ static void xics_spapr_initfn(Object *obj)
xics->ics = ICS(object_new(TYPE_ICS));
object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->icp = xics;
+ xics->ics->xics = xics;
}
static void xics_spapr_class_init(ObjectClass *oc, void *data)
@@ -328,14 +329,14 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
return -1;
}
-int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
+int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
Error **errp)
{
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
int irq;
if (irq_hint) {
- assert(src == xics_find_source(icp, irq_hint));
+ assert(src == xics_find_source(xics, irq_hint));
if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
return -1;
@@ -360,11 +361,11 @@ int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
* Allocate block of consecutive IRQs, and return the number of the first IRQ in
* the block. If align==true, aligns the first IRQ number to num.
*/
-int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
+int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
bool align, Error **errp)
{
int i, first = -1;
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
assert(src == 0);
/*
@@ -404,23 +405,23 @@ static void ics_free(ICSState *ics, int srcno, int num)
for (i = srcno; i < srcno + num; ++i) {
if (ICS_IRQ_FREE(ics, i)) {
- trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
+ trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
}
memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
}
}
-void xics_spapr_free(XICSState *icp, int irq, int num)
+void xics_spapr_free(XICSState *xics, int irq, int num)
{
- int src = xics_find_source(icp, irq);
+ int src = xics_find_source(xics, irq);
if (src >= 0) {
- ICSState *ics = &icp->ics[src];
+ ICSState *ics = &xics->ics[src];
/* FIXME: implement multiple sources */
assert(src == 0);
- trace_xics_ics_free(ics - icp->ics, irq, num);
+ trace_xics_ics_free(ics - xics->ics, irq, num);
ics_free(ics, irq - ics->offset, num);
}
}
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index a8d497c..d0454e4 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -116,16 +116,16 @@ static XICSState *try_create_xics(const char *type, int nr_servers,
static XICSState *xics_system_init(MachineState *machine,
int nr_servers, int nr_irqs, Error **errp)
{
- XICSState *icp = NULL;
+ XICSState *xics = NULL;
if (kvm_enabled()) {
Error *err = NULL;
if (machine_kernel_irqchip_allowed(machine)) {
- icp = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
- &err);
+ xics = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
+ &err);
}
- if (machine_kernel_irqchip_required(machine) && !icp) {
+ if (machine_kernel_irqchip_required(machine) && !xics) {
error_reportf_err(err,
"kernel_irqchip requested but unavailable: ");
} else {
@@ -133,11 +133,11 @@ static XICSState *xics_system_init(MachineState *machine,
}
}
- if (!icp) {
- icp = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
+ if (!xics) {
+ xics = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
}
- return icp;
+ return xics;
}
static int spapr_fixup_cpu_smt_dt(void *fdt, int offset, PowerPCCPU *cpu,
@@ -1780,9 +1780,9 @@ static void ppc_spapr_init(MachineState *machine)
load_limit = MIN(spapr->rma_size, RTAS_MAX_ADDR) - FW_OVERHEAD;
/* Set up Interrupt Controller before we create the VCPUs */
- spapr->icp = xics_system_init(machine,
- DIV_ROUND_UP(max_cpus * smt, smp_threads),
- XICS_IRQS_SPAPR, &error_fatal);
+ spapr->xics = xics_system_init(machine,
+ DIV_ROUND_UP(max_cpus * smt, smp_threads),
+ XICS_IRQS_SPAPR, &error_fatal);
if (smc->dr_lmb_enabled) {
spapr_validate_node_memory(machine, &error_fatal);
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 3a5da09..a57635a 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc/spapr_cpu_core.c
@@ -42,7 +42,7 @@ static void spapr_cpu_destroy(PowerPCCPU *cpu)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- xics_cpu_destroy(spapr->icp, cpu);
+ xics_cpu_destroy(spapr->xics, cpu);
qemu_unregister_reset(spapr_cpu_reset, cpu);
}
@@ -76,7 +76,7 @@ void spapr_cpu_init(sPAPRMachineState *spapr, PowerPCCPU *cpu, Error **errp)
}
}
- xics_cpu_setup(spapr->icp, cpu);
+ xics_cpu_setup(spapr->xics, cpu);
qemu_register_reset(spapr_cpu_reset, cpu);
spapr_cpu_reset(cpu);
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index 0585f8a..b0668b3 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -386,7 +386,7 @@ static void spapr_powerdown_req(Notifier *n, void *opaque)
rtas_event_log_queue(RTAS_LOG_TYPE_EPOW, new_epow, true);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
static void spapr_hotplug_set_signalled(uint32_t drc_index)
@@ -468,7 +468,7 @@ static void spapr_hotplug_req_event(uint8_t hp_id, uint8_t hp_action,
rtas_event_log_queue(RTAS_LOG_TYPE_HOTPLUG, new_hp, true);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
void spapr_hotplug_req_add_by_index(sPAPRDRConnector *drc)
@@ -551,7 +551,7 @@ static void check_exception(PowerPCCPU *cpu, sPAPRMachineState *spapr,
* interrupts.
*/
if (rtas_event_log_contains(mask, true)) {
- qemu_irq_pulse(xics_get_qirq(spapr->icp, spapr->check_exception_irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, spapr->check_exception_irq));
}
return;
@@ -603,7 +603,7 @@ out_no_events:
void spapr_events_init(sPAPRMachineState *spapr)
{
QTAILQ_INIT(&spapr->pending_events);
- spapr->check_exception_irq = xics_spapr_alloc(spapr->icp, 0, 0, false,
+ spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, 0, false,
&error_fatal);
spapr->epow_notifier.notify = spapr_powerdown_req;
qemu_register_powerdown_notifier(&spapr->epow_notifier);
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 451651d..8c1e6b1 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -322,7 +322,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
return;
}
- xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
+ xics_spapr_free(spapr->xics, msi->first_irq, msi->num);
if (msi_present(pdev)) {
spapr_msi_setmsg(pdev, 0, false, 0, 0);
}
@@ -360,7 +360,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
/* Allocate MSIs */
- irq = xics_spapr_alloc_block(spapr->icp, 0, req_num, false,
+ irq = xics_spapr_alloc_block(spapr->xics, 0, req_num, false,
ret_intr_type == RTAS_TYPE_MSI, &err);
if (err) {
error_reportf_err(err, "Can't allocate MSIs for device %x: ",
@@ -371,7 +371,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
/* Release previous MSIs */
if (msi) {
- xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
+ xics_spapr_free(spapr->xics, msi->first_irq, msi->num);
g_hash_table_remove(phb->msi, &config_addr);
}
@@ -733,7 +733,7 @@ static void spapr_msi_write(void *opaque, hwaddr addr,
trace_spapr_pci_msi_write(addr, data, irq);
- qemu_irq_pulse(xics_get_qirq(spapr->icp, irq));
+ qemu_irq_pulse(xics_get_qirq(spapr->xics, irq));
}
static const MemoryRegionOps spapr_msi_ops = {
@@ -1442,7 +1442,8 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
uint32_t irq;
Error *local_err = NULL;
- irq = xics_spapr_alloc_block(spapr->icp, 0, 1, true, false, &local_err);
+ irq = xics_spapr_alloc_block(spapr->xics, 0, 1, true, false,
+ &local_err);
if (local_err) {
error_propagate(errp, local_err);
error_prepend(errp, "can't allocate LSIs: ");
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index 7ffd23e..f93244d 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -463,7 +463,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
dev->qdev.id = id;
}
- dev->irq = xics_spapr_alloc(spapr->icp, 0, dev->irq, false, &local_err);
+ dev->irq = xics_spapr_alloc(spapr->xics, 0, dev->irq, false, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
index 7848366..288b89c 100644
--- a/include/hw/pci-host/spapr.h
+++ b/include/hw/pci-host/spapr.h
@@ -93,7 +93,7 @@ static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- return xics_get_qirq(spapr->icp, phb->lsi_table[pin].irq);
+ return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
}
PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index e1f8274..4932555 100644
--- a/include/hw/ppc/spapr.h
+++ b/include/hw/ppc/spapr.h
@@ -52,7 +52,7 @@ struct sPAPRMachineState {
struct VIOsPAPRBus *vio_bus;
QLIST_HEAD(, sPAPRPHBState) phbs;
struct sPAPRNVRAM *nvram;
- XICSState *icp;
+ XICSState *xics;
DeviceState *rtc;
void *htab;
diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h
index 5f8b042..bdb5d2f 100644
--- a/include/hw/ppc/spapr_vio.h
+++ b/include/hw/ppc/spapr_vio.h
@@ -90,7 +90,7 @@ static inline qemu_irq spapr_vio_qirq(VIOsPAPRDevice *dev)
{
sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
- return xics_get_qirq(spapr->icp, dev->irq);
+ return xics_get_qirq(spapr->xics, dev->irq);
}
static inline bool spapr_vio_dma_valid(VIOsPAPRDevice *dev, uint64_t taddr,
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 2a9b91d..c9f0ad7 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -142,7 +142,7 @@ struct ICSState {
uint32_t offset;
qemu_irq *qirqs;
ICSIRQState *irqs;
- XICSState *icp;
+ XICSState *xics;
};
static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (4 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 4:20 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 07/11] ppc/xics: An ICS with offset 0 is assumed to be uninitialized Nikunj A Dadhania
` (4 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Instead of an array of fixed sized blocks, use a list, as we will need
to have sources with variable number of interrupts. SPAPR only uses
a single entry. Native will create more. If performance becomes an
issue we can add some hashed lookup but for now this will do fine.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 78 +++++++++++++++++++++++++++---------------------
hw/intc/xics_kvm.c | 29 +++++++++++++-----
hw/intc/xics_spapr.c | 82 +++++++++++++++++++++++++++++----------------------
hw/ppc/spapr_events.c | 2 +-
hw/ppc/spapr_pci.c | 5 ++--
hw/ppc/spapr_vio.c | 2 +-
include/hw/ppc/xics.h | 13 ++++----
7 files changed, 124 insertions(+), 87 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 38e51fc..ef2a1e4 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -96,13 +96,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
static void xics_common_reset(DeviceState *d)
{
XICSState *xics = XICS_COMMON(d);
+ ICSState *ics;
int i;
for (i = 0; i < xics->nr_servers; i++) {
device_reset(DEVICE(&xics->ss[i]));
}
- device_reset(DEVICE(xics->ics));
+ QLIST_FOREACH(ics, &xics->ics, list) {
+ device_reset(DEVICE(ics));
+ }
}
static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
@@ -134,7 +137,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
}
assert(info->set_nr_irqs);
- assert(xics->ics);
info->set_nr_irqs(xics, value, errp);
}
@@ -212,33 +214,35 @@ static void ics_reject(ICSState *ics, int nr);
static void ics_resend(ICSState *ics);
static void ics_eoi(ICSState *ics, int nr);
-static void icp_check_ipi(XICSState *xics, int server)
+static void icp_check_ipi(ICPState *ss, int server)
{
- ICPState *ss = xics->ss + server;
-
if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
return;
}
trace_xics_icp_check_ipi(server, ss->mfrr);
- if (XISR(ss)) {
- ics_reject(xics->ics, XISR(ss));
+ if (XISR(ss) && ss->xirr_owner) {
+ ics_reject(ss->xirr_owner, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
ss->pending_priority = ss->mfrr;
+ ss->xirr_owner = NULL;
qemu_irq_raise(ss->output);
}
static void icp_resend(XICSState *xics, int server)
{
ICPState *ss = xics->ss + server;
+ ICSState *ics;
if (ss->mfrr < CPPR(ss)) {
- icp_check_ipi(xics, server);
+ icp_check_ipi(ss, server);
+ }
+ QLIST_FOREACH(ics, &xics->ics, list) {
+ ics_resend(ics);
}
- ics_resend(xics->ics);
}
void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
@@ -256,7 +260,10 @@ void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
ss->xirr &= ~XISR_MASK; /* Clear XISR */
ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
- ics_reject(xics->ics, old_xisr);
+ if (ss->xirr_owner) {
+ ics_reject(ss->xirr_owner, old_xisr);
+ ss->xirr_owner = NULL;
+ }
}
} else {
if (!XISR(ss)) {
@@ -271,7 +278,7 @@ void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)
ss->mfrr = mfrr;
if (mfrr < CPPR(ss)) {
- icp_check_ipi(xics, server);
+ icp_check_ipi(ss, server);
}
}
@@ -282,6 +289,7 @@ uint32_t icp_accept(ICPState *ss)
qemu_irq_lower(ss->output);
ss->xirr = ss->pending_priority << 24;
ss->pending_priority = 0xff;
+ ss->xirr_owner = NULL;
trace_xics_icp_accept(xirr, ss->xirr);
@@ -299,30 +307,40 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
void icp_eoi(XICSState *xics, int server, uint32_t xirr)
{
ICPState *ss = xics->ss + server;
+ ICSState *ics;
+ uint32_t irq;
/* Send EOI -> ICS */
ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
trace_xics_icp_eoi(server, xirr, ss->xirr);
- ics_eoi(xics->ics, xirr & XISR_MASK);
+ irq = xirr & XISR_MASK;
+ QLIST_FOREACH(ics, &xics->ics, list) {
+ if (ics_valid_irq(ics, irq)) {
+ ics_eoi(ics, irq);
+ }
+ }
if (!XISR(ss)) {
icp_resend(xics, server);
}
}
-static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)
+static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
{
+ XICSState *xics = ics->xics;
ICPState *ss = xics->ss + server;
trace_xics_icp_irq(server, nr, priority);
if ((priority >= CPPR(ss))
|| (XISR(ss) && (ss->pending_priority <= priority))) {
- ics_reject(xics->ics, nr);
+ ics_reject(ics, nr);
} else {
- if (XISR(ss)) {
- ics_reject(xics->ics, XISR(ss));
+ if (XISR(ss) && ss->xirr_owner) {
+ ics_reject(ss->xirr_owner, XISR(ss));
+ ss->xirr_owner = NULL;
}
ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
+ ss->xirr_owner = ics;
ss->pending_priority = priority;
trace_xics_icp_raise(ss->xirr, ss->pending_priority);
qemu_irq_raise(ss->output);
@@ -405,8 +423,7 @@ static void resend_msi(ICSState *ics, int srcno)
if (irq->status & XICS_STATUS_REJECTED) {
irq->status &= ~XICS_STATUS_REJECTED;
if (irq->priority != 0xff) {
- icp_irq(ics->xics, irq->server, srcno + ics->offset,
- irq->priority);
+ icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
}
}
@@ -419,7 +436,7 @@ static void resend_lsi(ICSState *ics, int srcno)
&& (irq->status & XICS_STATUS_ASSERTED)
&& !(irq->status & XICS_STATUS_SENT)) {
irq->status |= XICS_STATUS_SENT;
- icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
}
@@ -434,7 +451,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
irq->status |= XICS_STATUS_MASKED_PENDING;
trace_xics_masked_pending();
} else {
- icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
}
}
@@ -473,7 +490,7 @@ static void write_xive_msi(ICSState *ics, int srcno)
}
irq->status &= ~XICS_STATUS_MASKED_PENDING;
- icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
+ icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
static void write_xive_lsi(ICSState *ics, int srcno)
@@ -659,28 +676,23 @@ static const TypeInfo ics_info = {
/*
* Exported functions
*/
-int xics_find_source(XICSState *xics, int irq)
+ICSState *xics_find_source(XICSState *xics, int irq)
{
- int sources = 1;
- int src;
+ ICSState *ics;
- /* FIXME: implement multiple sources */
- for (src = 0; src < sources; ++src) {
- ICSState *ics = &xics->ics[src];
+ QLIST_FOREACH(ics, &xics->ics, list) {
if (ics_valid_irq(ics, irq)) {
- return src;
+ return ics;
}
}
-
- return -1;
+ return NULL;
}
qemu_irq xics_get_qirq(XICSState *xics, int irq)
{
- int src = xics_find_source(xics, irq);
+ ICSState *ics = xics_find_source(xics, irq);
- if (src >= 0) {
- ICSState *ics = &xics->ics[src];
+ if (ics) {
return ics->qirqs[irq - ics->offset];
}
diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
index 64d2256..75b3290 100644
--- a/hw/intc/xics_kvm.c
+++ b/hw/intc/xics_kvm.c
@@ -365,7 +365,13 @@ static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
Error **errp)
{
- xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
+ ICSState *ics = QLIST_FIRST(&xics->ics);
+
+ /* This needs to be deprecated ... */
+ xics->nr_irqs = nr_irqs;
+ if (ics) {
+ ics->nr_irqs = nr_irqs;
+ }
}
static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
@@ -398,6 +404,7 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
{
KVMXICSState *xicskvm = KVM_XICS(dev);
XICSState *xics = XICS_COMMON(dev);
+ ICSState *ics;
int i, rc;
Error *error = NULL;
struct kvm_create_device xics_create_device = {
@@ -449,10 +456,12 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
xicskvm->kernel_xics_fd = xics_create_device.fd;
- object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
- if (error) {
- error_propagate(errp, error);
- goto fail;
+ QLIST_FOREACH(ics, &xics->ics, list) {
+ object_property_set_bool(OBJECT(ics), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ goto fail;
+ }
}
assert(xics->nr_servers);
@@ -481,10 +490,14 @@ fail:
static void xics_kvm_initfn(Object *obj)
{
XICSState *xics = XICS_COMMON(obj);
+ ICSState *ics;
+
+ QLIST_INIT(&xics->ics);
- xics->ics = ICS(object_new(TYPE_KVM_ICS));
- object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->xics = xics;
+ ics = ICS(object_new(TYPE_KVM_ICS));
+ object_property_add_child(obj, "ics", OBJECT(ics), NULL);
+ ics->xics = xics;
+ QLIST_INSERT_HEAD(&xics->ics, ics, list);
}
static void xics_kvm_class_init(ObjectClass *oc, void *data)
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index eda15a6..b03dd0d 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -113,10 +113,10 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->xics->ics;
+ ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
uint32_t nr, server, priority;
- if ((nargs != 3) || (nret != 1)) {
+ if ((nargs != 3) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
@@ -141,10 +141,10 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->xics->ics;
+ ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
uint32_t nr;
- if ((nargs != 1) || (nret != 3)) {
+ if ((nargs != 1) || (nret != 3) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
@@ -166,10 +166,10 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->xics->ics;
+ ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
uint32_t nr;
- if ((nargs != 1) || (nret != 1)) {
+ if ((nargs != 1) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
@@ -192,10 +192,10 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nargs, target_ulong args,
uint32_t nret, target_ulong rets)
{
- ICSState *ics = spapr->xics->ics;
+ ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
uint32_t nr;
- if ((nargs != 1) || (nret != 1)) {
+ if ((nargs != 1) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
@@ -217,7 +217,13 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
Error **errp)
{
- xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
+ ICSState *ics = QLIST_FIRST(&xics->ics);
+
+ /* This needs to be deprecated ... */
+ xics->nr_irqs = nr_irqs;
+ if (ics) {
+ ics->nr_irqs = nr_irqs;
+ }
}
static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
@@ -240,6 +246,7 @@ static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
static void xics_spapr_realize(DeviceState *dev, Error **errp)
{
XICSState *xics = XICS(dev);
+ ICSState *ics;
Error *error = NULL;
int i;
@@ -261,10 +268,12 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
spapr_register_hypercall(H_EOI, h_eoi);
spapr_register_hypercall(H_IPOLL, h_ipoll);
- object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
- if (error) {
- error_propagate(errp, error);
- return;
+ QLIST_FOREACH(ics, &xics->ics, list) {
+ object_property_set_bool(OBJECT(ics), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
}
for (i = 0; i < xics->nr_servers; i++) {
@@ -280,10 +289,14 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
static void xics_spapr_initfn(Object *obj)
{
XICSState *xics = XICS(obj);
+ ICSState *ics;
+
+ QLIST_INIT(&xics->ics);
- xics->ics = ICS(object_new(TYPE_ICS));
- object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
- xics->ics->xics = xics;
+ ics = ICS(object_new(TYPE_ICS));
+ object_property_add_child(obj, "ics", OBJECT(ics), NULL);
+ ics->xics = xics;
+ QLIST_INSERT_HEAD(&xics->ics, ics, list);
}
static void xics_spapr_class_init(ObjectClass *oc, void *data)
@@ -329,14 +342,15 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
return -1;
}
-int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
- Error **errp)
+int xics_spapr_alloc(XICSState *xics, int irq_hint, bool lsi, Error **errp)
{
- ICSState *ics = &xics->ics[src];
+ ICSState *ics = QLIST_FIRST(&xics->ics);
int irq;
+ if (!ics) {
+ return -1;
+ }
if (irq_hint) {
- assert(src == xics_find_source(xics, irq_hint));
if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
return -1;
@@ -352,7 +366,7 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
}
ics_set_irq_type(ics, irq - ics->offset, lsi);
- trace_xics_alloc(src, irq);
+ trace_xics_alloc(0, irq);
return irq;
}
@@ -361,13 +375,16 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
* Allocate block of consecutive IRQs, and return the number of the first IRQ in
* the block. If align==true, aligns the first IRQ number to num.
*/
-int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
- bool align, Error **errp)
+int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align,
+ Error **errp)
{
+ ICSState *ics = QLIST_FIRST(&xics->ics);
int i, first = -1;
- ICSState *ics = &xics->ics[src];
- assert(src == 0);
+ if (!ics) {
+ return -1;
+ }
+
/*
* MSIMesage::data is used for storing VIRQ so
* it has to be aligned to num to support multiple
@@ -394,7 +411,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
}
first += ics->offset;
- trace_xics_alloc_block(src, first, num, lsi, align);
+ trace_xics_alloc_block(0, first, num, lsi, align);
return first;
}
@@ -405,7 +422,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
for (i = srcno; i < srcno + num; ++i) {
if (ICS_IRQ_FREE(ics, i)) {
- trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
+ trace_xics_ics_free_warn(0, i + ics->offset);
}
memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
}
@@ -413,15 +430,10 @@ static void ics_free(ICSState *ics, int srcno, int num)
void xics_spapr_free(XICSState *xics, int irq, int num)
{
- int src = xics_find_source(xics, irq);
-
- if (src >= 0) {
- ICSState *ics = &xics->ics[src];
-
- /* FIXME: implement multiple sources */
- assert(src == 0);
+ ICSState *ics = xics_find_source(xics, irq);
- trace_xics_ics_free(ics - xics->ics, irq, num);
+ if (ics) {
+ trace_xics_ics_free(0, irq, num);
ics_free(ics, irq - ics->offset, num);
}
}
diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
index b0668b3..adf8da4 100644
--- a/hw/ppc/spapr_events.c
+++ b/hw/ppc/spapr_events.c
@@ -603,7 +603,7 @@ out_no_events:
void spapr_events_init(sPAPRMachineState *spapr)
{
QTAILQ_INIT(&spapr->pending_events);
- spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, 0, false,
+ spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, false,
&error_fatal);
spapr->epow_notifier.notify = spapr_powerdown_req;
qemu_register_powerdown_notifier(&spapr->epow_notifier);
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 8c1e6b1..3d08c0a 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -360,7 +360,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
}
/* Allocate MSIs */
- irq = xics_spapr_alloc_block(spapr->xics, 0, req_num, false,
+ irq = xics_spapr_alloc_block(spapr->xics, req_num, false,
ret_intr_type == RTAS_TYPE_MSI, &err);
if (err) {
error_reportf_err(err, "Can't allocate MSIs for device %x: ",
@@ -1442,8 +1442,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
uint32_t irq;
Error *local_err = NULL;
- irq = xics_spapr_alloc_block(spapr->xics, 0, 1, true, false,
- &local_err);
+ irq = xics_spapr_alloc_block(spapr->xics, 1, true, false, &local_err);
if (local_err) {
error_propagate(errp, local_err);
error_prepend(errp, "can't allocate LSIs: ");
diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
index f93244d..22360af 100644
--- a/hw/ppc/spapr_vio.c
+++ b/hw/ppc/spapr_vio.c
@@ -463,7 +463,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
dev->qdev.id = id;
}
- dev->irq = xics_spapr_alloc(spapr->xics, 0, dev->irq, false, &local_err);
+ dev->irq = xics_spapr_alloc(spapr->xics, dev->irq, false, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index c9f0ad7..be96fd8 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -83,7 +83,7 @@ struct XICSState {
uint32_t nr_servers;
uint32_t nr_irqs;
ICPState *ss;
- ICSState *ics;
+ QLIST_HEAD(, ICSState) ics;
};
#define TYPE_ICP "icp"
@@ -109,6 +109,7 @@ struct ICPState {
DeviceState parent_obj;
/*< public >*/
CPUState *cs;
+ ICSState *xirr_owner;
uint32_t xirr;
uint8_t pending_priority;
uint8_t mfrr;
@@ -143,6 +144,7 @@ struct ICSState {
qemu_irq *qirqs;
ICSIRQState *irqs;
XICSState *xics;
+ QLIST_ENTRY(ICSState) list;
};
static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
@@ -170,10 +172,9 @@ struct ICSIRQState {
#define XICS_IRQS_SPAPR 1024
qemu_irq xics_get_qirq(XICSState *icp, int irq);
-int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
- Error **errp);
-int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
- bool align, Error **errp);
+int xics_spapr_alloc(XICSState *icp, int irq_hint, bool lsi, Error **errp);
+int xics_spapr_alloc_block(XICSState *icp, int num, bool lsi, bool align,
+ Error **errp);
void xics_spapr_free(XICSState *icp, int irq, int num);
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
@@ -193,6 +194,6 @@ void ics_write_xive(ICSState *ics, int nr, int server,
void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
-int xics_find_source(XICSState *icp, int irq);
+ICSState *xics_find_source(XICSState *icp, int irq);
#endif /* __XICS_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 07/11] ppc/xics: An ICS with offset 0 is assumed to be uninitialized
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (5 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS Nikunj A Dadhania
` (3 subsequent siblings)
10 siblings, 0 replies; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This will make life easier for dealing with dynamically configured
ICSes such as PHB3
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
include/hw/ppc/xics.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index be96fd8..3c63c36 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -149,7 +149,7 @@ struct ICSState {
static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
{
- return (nr >= ics->offset)
+ return (ics->offset != 0) && (nr >= ics->offset)
&& (nr < (ics->offset + ics->nr_irqs));
}
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (6 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 07/11] ppc/xics: An ICS with offset 0 is assumed to be uninitialized Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 4:21 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class Nikunj A Dadhania
` (2 subsequent siblings)
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
[Move object allocation and adding child to the helper]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 10 ++++++++++
hw/intc/xics_spapr.c | 7 +------
include/hw/ppc/xics.h | 1 +
3 files changed, 12 insertions(+), 6 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index ef2a1e4..326d21f 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -108,6 +108,16 @@ static void xics_common_reset(DeviceState *d)
}
}
+void xics_add_ics(XICSState *xics)
+{
+ ICSState *ics;
+
+ ics = ICS(object_new(TYPE_ICS));
+ object_property_add_child(OBJECT(xics), "ics", OBJECT(ics), NULL);
+ ics->xics = xics;
+ QLIST_INSERT_HEAD(&xics->ics, ics, list);
+}
+
static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index b03dd0d..8acafd9 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -289,14 +289,9 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
static void xics_spapr_initfn(Object *obj)
{
XICSState *xics = XICS(obj);
- ICSState *ics;
QLIST_INIT(&xics->ics);
-
- ics = ICS(object_new(TYPE_ICS));
- object_property_add_child(obj, "ics", OBJECT(ics), NULL);
- ics->xics = xics;
- QLIST_INSERT_HEAD(&xics->ics, ics, list);
+ xics_add_ics(xics);
}
static void xics_spapr_class_init(ObjectClass *oc, void *data)
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 3c63c36..ee0fce2 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -195,5 +195,6 @@ void ics_write_xive(ICSState *ics, int nr, int server,
void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
ICSState *xics_find_source(XICSState *icp, int irq);
+void xics_add_ics(XICSState *xics);
#endif /* __XICS_H__ */
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (7 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 4:26 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command Nikunj A Dadhania
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
The existing implementation remains same and ics-base is introduced.
This will allow different implementations for the source controllers
such as the MSI support of PHB3 on Power8 which uses in-memory state
tables for example.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
hw/intc/xics_spapr.c | 36 ++++++++++--------
include/hw/ppc/xics.h | 11 +++++-
3 files changed, 97 insertions(+), 51 deletions(-)
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index 326d21f..e2aa48d 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
#define XISR(ss) (((ss)->xirr) & XISR_MASK)
#define CPPR(ss) (((ss)->xirr) >> 24)
-static void ics_reject(ICSState *ics, int nr);
-static void ics_resend(ICSState *ics);
-static void ics_eoi(ICSState *ics, int nr);
+static void ics_base_reject(ICSState *ics, uint32_t nr)
+{
+ ICSStateClass *k = ICS_GET_CLASS(ics);
+
+ if (k->reject) {
+ k->reject(ics, nr);
+ }
+}
+
+static void ics_base_resend(ICSState *ics)
+{
+ ICSStateClass *k = ICS_GET_CLASS(ics);
+
+ if (k->resend) {
+ k->resend(ics);
+ }
+}
+
+static void ics_base_eoi(ICSState *ics, int nr)
+{
+ ICSStateClass *k = ICS_GET_CLASS(ics);
+
+ if (k->eoi) {
+ k->eoi(ics, nr);
+ }
+}
static void icp_check_ipi(ICPState *ss, int server)
{
@@ -233,7 +256,7 @@ static void icp_check_ipi(ICPState *ss, int server)
trace_xics_icp_check_ipi(server, ss->mfrr);
if (XISR(ss) && ss->xirr_owner) {
- ics_reject(ss->xirr_owner, XISR(ss));
+ ics_base_reject(ss->xirr_owner, XISR(ss));
}
ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
@@ -251,7 +274,7 @@ static void icp_resend(XICSState *xics, int server)
icp_check_ipi(ss, server);
}
QLIST_FOREACH(ics, &xics->ics, list) {
- ics_resend(ics);
+ ics_base_resend(ics);
}
}
@@ -271,7 +294,7 @@ void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
ss->pending_priority = 0xff;
qemu_irq_lower(ss->output);
if (ss->xirr_owner) {
- ics_reject(ss->xirr_owner, old_xisr);
+ ics_base_reject(ss->xirr_owner, old_xisr);
ss->xirr_owner = NULL;
}
}
@@ -325,8 +348,8 @@ void icp_eoi(XICSState *xics, int server, uint32_t xirr)
trace_xics_icp_eoi(server, xirr, ss->xirr);
irq = xirr & XISR_MASK;
QLIST_FOREACH(ics, &xics->ics, list) {
- if (ics_valid_irq(ics, irq)) {
- ics_eoi(ics, irq);
+ if (ics_base_valid_irq(ics, irq)) {
+ ics_base_eoi(ics, irq);
}
}
if (!XISR(ss)) {
@@ -343,10 +366,10 @@ static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
if ((priority >= CPPR(ss))
|| (XISR(ss) && (ss->pending_priority <= priority))) {
- ics_reject(ics, nr);
+ ics_base_reject(ics, nr);
} else {
if (XISR(ss) && ss->xirr_owner) {
- ics_reject(ss->xirr_owner, XISR(ss));
+ ics_base_reject(ss->xirr_owner, XISR(ss));
ss->xirr_owner = NULL;
}
ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
@@ -425,7 +448,7 @@ static const TypeInfo icp_info = {
/*
* ICS: Source layer
*/
-static void resend_msi(ICSState *ics, int srcno)
+static void ics_resend_msi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -438,7 +461,7 @@ static void resend_msi(ICSState *ics, int srcno)
}
}
-static void resend_lsi(ICSState *ics, int srcno)
+static void ics_resend_lsi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -450,7 +473,7 @@ static void resend_lsi(ICSState *ics, int srcno)
}
}
-static void set_irq_msi(ICSState *ics, int srcno, int val)
+static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -466,7 +489,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
}
}
-static void set_irq_lsi(ICSState *ics, int srcno, int val)
+static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -476,7 +499,7 @@ static void set_irq_lsi(ICSState *ics, int srcno, int val)
} else {
irq->status &= ~XICS_STATUS_ASSERTED;
}
- resend_lsi(ics, srcno);
+ ics_resend_lsi(ics, srcno);
}
static void ics_set_irq(void *opaque, int srcno, int val)
@@ -484,13 +507,13 @@ static void ics_set_irq(void *opaque, int srcno, int val)
ICSState *ics = (ICSState *)opaque;
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
- set_irq_lsi(ics, srcno, val);
+ ics_set_irq_lsi(ics, srcno, val);
} else {
- set_irq_msi(ics, srcno, val);
+ ics_set_irq_msi(ics, srcno, val);
}
}
-static void write_xive_msi(ICSState *ics, int srcno)
+static void ics_write_xive_msi(ICSState *ics, int srcno)
{
ICSIRQState *irq = ics->irqs + srcno;
@@ -503,31 +526,30 @@ static void write_xive_msi(ICSState *ics, int srcno)
icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
}
-static void write_xive_lsi(ICSState *ics, int srcno)
+static void ics_write_xive_lsi(ICSState *ics, int srcno)
{
- resend_lsi(ics, srcno);
+ ics_resend_lsi(ics, srcno);
}
-void ics_write_xive(ICSState *ics, int nr, int server,
- uint8_t priority, uint8_t saved_priority)
+void ics_write_xive(ICSState *ics, int srcno, int server,
+ uint8_t priority, uint8_t saved_priority)
{
- int srcno = nr - ics->offset;
ICSIRQState *irq = ics->irqs + srcno;
irq->server = server;
irq->priority = priority;
irq->saved_priority = saved_priority;
- trace_xics_ics_write_xive(nr, srcno, server, priority);
+ trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
- write_xive_lsi(ics, srcno);
+ ics_write_xive_lsi(ics, srcno);
} else {
- write_xive_msi(ics, srcno);
+ ics_write_xive_msi(ics, srcno);
}
}
-static void ics_reject(ICSState *ics, int nr)
+static void ics_reject(ICSState *ics, uint32_t nr)
{
ICSIRQState *irq = ics->irqs + nr - ics->offset;
@@ -543,14 +565,14 @@ static void ics_resend(ICSState *ics)
for (i = 0; i < ics->nr_irqs; i++) {
/* FIXME: filter by server#? */
if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
- resend_lsi(ics, i);
+ ics_resend_lsi(ics, i);
} else {
- resend_msi(ics, i);
+ ics_resend_msi(ics, i);
}
}
}
-static void ics_eoi(ICSState *ics, int nr)
+static void ics_eoi(ICSState *ics, uint32_t nr)
{
int srcno = nr - ics->offset;
ICSIRQState *irq = ics->irqs + srcno;
@@ -639,7 +661,8 @@ static const VMStateDescription vmstate_ics = {
VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
- vmstate_ics_irq, ICSIRQState),
+ vmstate_ics_irq,
+ ICSIRQState),
VMSTATE_END_OF_LIST()
},
};
@@ -672,17 +695,28 @@ static void ics_class_init(ObjectClass *klass, void *data)
dc->vmsd = &vmstate_ics;
dc->reset = ics_reset;
isc->post_load = ics_post_load;
+ isc->reject = ics_reject;
+ isc->resend = ics_resend;
+ isc->eoi = ics_eoi;
}
static const TypeInfo ics_info = {
.name = TYPE_ICS,
- .parent = TYPE_DEVICE,
+ .parent = TYPE_ICS_BASE,
.instance_size = sizeof(ICSState),
.class_init = ics_class_init,
.class_size = sizeof(ICSStateClass),
.instance_init = ics_initfn,
};
+static const TypeInfo ics_base_info = {
+ .name = TYPE_ICS_BASE,
+ .parent = TYPE_DEVICE,
+ .abstract = true,
+ .instance_size = sizeof(ICSState),
+ .class_size = sizeof(ICSStateClass),
+};
+
/*
* Exported functions
*/
@@ -691,7 +725,7 @@ ICSState *xics_find_source(XICSState *xics, int irq)
ICSState *ics;
QLIST_FOREACH(ics, &xics->ics, list) {
- if (ics_valid_irq(ics, irq)) {
+ if (ics_base_valid_irq(ics, irq)) {
return ics;
}
}
@@ -721,6 +755,7 @@ static void xics_register_types(void)
{
type_register_static(&xics_common_info);
type_register_static(&ics_info);
+ type_register_static(&ics_base_info);
type_register_static(&icp_info);
}
diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
index 8acafd9..113b067 100644
--- a/hw/intc/xics_spapr.c
+++ b/hw/intc/xics_spapr.c
@@ -114,7 +114,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nret, target_ulong rets)
{
ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
- uint32_t nr, server, priority;
+ uint32_t nr, srcno, server, priority;
if ((nargs != 3) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -125,13 +125,14 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
priority = rtas_ld(args, 2);
- if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
+ if (!ics_base_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
|| (priority > 0xff)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
- ics_write_xive(ics, nr, server, priority, priority);
+ srcno = nr - ics->offset;
+ ics_write_xive(ics, srcno, server, priority, priority);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
@@ -142,7 +143,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nret, target_ulong rets)
{
ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
- uint32_t nr;
+ uint32_t nr, srcno;
if ((nargs != 1) || (nret != 3) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -151,14 +152,15 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
nr = rtas_ld(args, 0);
- if (!ics_valid_irq(ics, nr)) {
+ if (!ics_base_valid_irq(ics, nr)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
- rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
- rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
+ srcno = nr - ics->offset;
+ rtas_st(rets, 1, ics->irqs[srcno].server);
+ rtas_st(rets, 2, ics->irqs[srcno].priority);
}
static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
@@ -167,7 +169,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nret, target_ulong rets)
{
ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
- uint32_t nr;
+ uint32_t nr, srcno;
if ((nargs != 1) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -176,13 +178,14 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
nr = rtas_ld(args, 0);
- if (!ics_valid_irq(ics, nr)) {
+ if (!ics_base_valid_irq(ics, nr)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
- ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
- ics->irqs[nr - ics->offset].priority);
+ srcno = nr - ics->offset;
+ ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
+ ics->irqs[srcno].priority);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
@@ -193,7 +196,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
uint32_t nret, target_ulong rets)
{
ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
- uint32_t nr;
+ uint32_t nr, srcno;
if ((nargs != 1) || (nret != 1) || !ics) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
@@ -202,14 +205,15 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
nr = rtas_ld(args, 0);
- if (!ics_valid_irq(ics, nr)) {
+ if (!ics_base_valid_irq(ics, nr)) {
rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
return;
}
- ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
- ics->irqs[nr - ics->offset].saved_priority,
- ics->irqs[nr - ics->offset].saved_priority);
+ srcno = nr - ics->offset;
+ ics_write_xive(ics, srcno, ics->irqs[srcno].server,
+ ics->irqs[srcno].saved_priority,
+ ics->irqs[srcno].saved_priority);
rtas_st(rets, 0, RTAS_OUT_SUCCESS);
}
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index ee0fce2..6fb1cb4 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -117,6 +117,10 @@ struct ICPState {
bool cap_irq_xics_enabled;
};
+#define TYPE_ICS_BASE "ics-base"
+#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
+
+/* Retain ics for sPAPR for migration from existing sPAPR guests */
#define TYPE_ICS "ics"
#define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
@@ -133,6 +137,9 @@ struct ICSStateClass {
void (*pre_save)(ICSState *s);
int (*post_load)(ICSState *s, int version_id);
+ void (*reject)(ICSState *s, uint32_t irq);
+ void (*resend)(ICSState *s);
+ void (*eoi)(ICSState *s, uint32_t irq);
};
struct ICSState {
@@ -147,7 +154,7 @@ struct ICSState {
QLIST_ENTRY(ICSState) list;
};
-static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
+static inline bool ics_base_valid_irq(ICSState *ics, uint32_t nr)
{
return (ics->offset != 0) && (nr >= ics->offset)
&& (nr < (ics->offset + ics->nr_irqs));
@@ -190,7 +197,7 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
void icp_eoi(XICSState *icp, int server, uint32_t xirr);
void ics_write_xive(ICSState *ics, int nr, int server,
- uint8_t priority, uint8_t saved_priority);
+ uint8_t priority, uint8_t saved_priority);
void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (8 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 4:36 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command Nikunj A Dadhania
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This provides MMIO based ICP access as found on POWER8
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
default-configs/ppc64-softmmu.mak | 3 +-
hw/intc/Makefile.objs | 1 +
hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++++++++
include/hw/ppc/xics.h | 14 ++
4 files changed, 312 insertions(+), 1 deletion(-)
create mode 100644 hw/intc/xics_native.c
diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
index c4be59f..315e30b 100644
--- a/default-configs/ppc64-softmmu.mak
+++ b/default-configs/ppc64-softmmu.mak
@@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=y
CONFIG_ETSEC=y
CONFIG_LIBDECNUMBER=y
# For pSeries
-CONFIG_XICS=$(CONFIG_PSERIES)
+CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV))
CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
+CONFIG_XICS_NATIVE=$(CONFIG_POWERNV)
CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
# For PReP
CONFIG_MC146818RTC=y
diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
index 530df2e..f8bbeda 100644
--- a/hw/intc/Makefile.objs
+++ b/hw/intc/Makefile.objs
@@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
obj-$(CONFIG_SH4) += sh_intc.o
obj-$(CONFIG_XICS) += xics.o
obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
+obj-$(CONFIG_XICS_NATIVE) += xics_native.o
obj-$(CONFIG_XICS_KVM) += xics_kvm.o
obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
obj-$(CONFIG_S390_FLIC) += s390_flic.o
diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c
new file mode 100644
index 0000000..26e45cc
--- /dev/null
+++ b/hw/intc/xics_native.c
@@ -0,0 +1,295 @@
+/*
+ * QEMU PowerPC hardware System Emulator
+ *
+ * Native version of ICS/ICP
+ *
+ * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ */
+
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "trace.h"
+#include "qemu/timer.h"
+#include "hw/ppc/xics.h"
+#include "qapi/visitor.h"
+#include "qapi/error.h"
+
+#include <libfdt.h>
+
+/* #define DEBUG_MM(fmt...) printf(fmt) */
+#define DEBUG_MM(fmt...) do { } while (0)
+
+static void xics_native_initfn(Object *obj)
+{
+ XICSState *xics = XICS_NATIVE(obj);
+
+ QLIST_INIT(&xics->ics);
+}
+
+static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width)
+{
+ XICSState *s = opaque;
+ int32_t cpu_id, server;
+ uint32_t val;
+ ICPState *ss;
+ bool byte0 = (width == 1 && (addr & 0x3) == 0);
+
+ cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
+ server = get_cpu_index_by_dt_id(cpu_id);
+ if (server < 0) {
+ fprintf(stderr, "XICS: Bad ICP server %d\n", server);
+ goto bad_access;
+ }
+ ss = &s->ss[server];
+
+ switch (addr & 0xffc) {
+ case 0: /* poll */
+ val = icp_ipoll(ss, NULL);
+ if (byte0) {
+ val >>= 24;
+ } else if (width != 4) {
+ goto bad_access;
+ }
+ break;
+ case 4: /* xirr */
+ if (byte0) {
+ val = icp_ipoll(ss, NULL) >> 24;
+ } else if (width == 4) {
+ val = icp_accept(ss);
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 12:
+ if (byte0) {
+ val = ss->mfrr;
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 16:
+ if (width == 4) {
+ val = ss->links[0];
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 20:
+ if (width == 4) {
+ val = ss->links[1];
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 24:
+ if (width == 4) {
+ val = ss->links[2];
+ } else {
+ goto bad_access;
+ }
+ break;
+ default:
+bad_access:
+ fprintf(stderr, "XICS: Bad ICP access %llx/%d\n",
+ (unsigned long long)addr, width);
+ val = 0xffffffff;
+ }
+ DEBUG_MM("icp_mm_read(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
+ (unsigned long long)addr, cpu_id, server, (int)(addr & 0xffc),
+ width, val);
+
+ return val;
+}
+
+static void icp_mm_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned width)
+{
+ XICSState *s = opaque;
+ int32_t cpu_id, server;
+ ICPState *ss;
+ bool byte0 = (width == 1 && (addr & 0x3) == 0);
+
+ cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
+ server = get_cpu_index_by_dt_id(cpu_id);
+ if (server < 0) {
+ fprintf(stderr, "XICS: Bad ICP server %d\n", server);
+ goto bad_access;
+ }
+ ss = &s->ss[server];
+
+ DEBUG_MM("icp_mm_write(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
+ (unsigned long long)addr, cpu_id, server,
+ (int)(addr & 0xffc), width, (uint32_t)val);
+
+ switch (addr & 0xffc) {
+ case 4: /* xirr */
+ if (byte0) {
+ icp_set_cppr(s, server, val);
+ } else if (width == 4) {
+ icp_eoi(s, server, val);
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 12:
+ if (byte0) {
+ icp_set_mfrr(s, server, val);
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 16:
+ if (width == 4) {
+ ss->links[0] = val;
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 20:
+ if (width == 4) {
+ ss->links[1] = val;
+ } else {
+ goto bad_access;
+ }
+ break;
+ case 24:
+ if (width == 4) {
+ ss->links[2] = val;
+ } else {
+ goto bad_access;
+ }
+ break;
+ default:
+ bad_access:
+ val = 0xffffffff;
+ }
+}
+
+static const MemoryRegionOps icp_mm_ops = {
+ .read = icp_mm_read,
+ .write = icp_mm_write,
+ .valid.min_access_size = 1,
+ .valid.max_access_size = 4,
+ .impl.min_access_size = 1,
+ .impl.max_access_size = 4,
+ .endianness = DEVICE_BIG_ENDIAN,
+};
+
+#define _FDT(exp) \
+ do { \
+ int ret = (exp); \
+ if (ret < 0) { \
+ fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
+ #exp, fdt_strerror(ret)); \
+ exit(1); \
+ } \
+ } while (0)
+
+void xics_create_native_icp_node(XICSState *s, void *fdt,
+ uint32_t base, uint32_t count)
+{
+ uint64_t addr;
+ char *name;
+ const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
+ uint32_t irange[2], i, rsize;
+ uint64_t *reg;
+
+ addr = ICP_MM_BASE | (base << 12);
+
+ irange[0] = cpu_to_be32(base);
+ irange[1] = cpu_to_be32(count);
+
+ rsize = sizeof(uint64_t) * 2 * count;
+ reg = g_malloc(rsize);
+ for (i = 0; i < count; i++) {
+ reg[i * 2] = cpu_to_be64(addr | ((base + i) * 0x1000));
+ reg[i * 2 + 1] = cpu_to_be64(0x1000);
+ }
+
+ name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
+
+ /* interrupt controller */
+ _FDT((fdt_begin_node(fdt, name)));
+ g_free(name);
+
+ _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat))));
+ _FDT((fdt_property(fdt, "reg", reg, rsize)));
+ _FDT((fdt_property_string(fdt, "device_type",
+ "PowerPC-External-Interrupt-Presentation")));
+ _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
+ _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
+ irange, sizeof(irange))));
+ _FDT((fdt_property_cell(fdt, "#interrupt-cells", 1)));
+ _FDT((fdt_property_cell(fdt, "#address-cells", 0)));
+ _FDT((fdt_end_node(fdt)));
+}
+
+static void xics_native_realize(DeviceState *dev, Error **errp)
+{
+ XICSState *s = XICS_NATIVE(dev);
+ SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
+ Error *error = NULL;
+ int i;
+
+ if (!s->nr_servers) {
+ error_setg(errp, "Number of servers needs to be greater 0");
+ return;
+ }
+
+ /* Register MMIO regions */
+ memory_region_init_io(&s->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp",
+ ICP_MM_SIZE);
+ sysbus_init_mmio(sbd, &s->icp_mmio);
+ sysbus_mmio_map(sbd, 0, ICP_MM_BASE);
+
+ for (i = 0; i < s->nr_servers; i++) {
+ object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &error);
+ if (error) {
+ error_propagate(errp, error);
+ return;
+ }
+ }
+}
+
+static void xics_native_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+ XICSStateClass *xsc = XICS_NATIVE_CLASS(oc);
+
+ dc->realize = xics_native_realize;
+ xsc->set_nr_servers = xics_set_nr_servers;
+}
+
+static const TypeInfo xics_native_info = {
+ .name = TYPE_XICS_NATIVE,
+ .parent = TYPE_XICS_COMMON,
+ .instance_size = sizeof(XICSState),
+ .class_size = sizeof(XICSStateClass),
+ .class_init = xics_native_class_init,
+ .instance_init = xics_native_initfn,
+};
+
+static void xics_native_register_types(void)
+{
+ type_register_static(&xics_native_info);
+}
+type_init(xics_native_register_types)
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 6fb1cb4..0e47ecb 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -42,6 +42,9 @@
#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
+#define TYPE_XICS_NATIVE "xics-native"
+#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE)
+
#define XICS_COMMON_CLASS(klass) \
OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
#define XICS_SPAPR_CLASS(klass) \
@@ -50,6 +53,8 @@
OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
#define XICS_SPAPR_GET_CLASS(obj) \
OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
+#define XICS_NATIVE_CLASS(klass) \
+ OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_NATIVE)
#define XICS_IPI 0x2
#define XICS_BUID 0x1
@@ -84,6 +89,7 @@ struct XICSState {
uint32_t nr_irqs;
ICPState *ss;
QLIST_HEAD(, ICSState) ics;
+ MemoryRegion icp_mmio;
};
#define TYPE_ICP "icp"
@@ -115,8 +121,13 @@ struct ICPState {
uint8_t mfrr;
qemu_irq output;
bool cap_irq_xics_enabled;
+ uint32_t links[3];
};
+/* This should be an XSCOM BAR ... the size is arbitrary as well */
+#define ICP_MM_BASE 0x0003FFFF80000000
+#define ICP_MM_SIZE 0x0000000010000000
+
#define TYPE_ICS_BASE "ics-base"
#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
@@ -187,6 +198,9 @@ void xics_spapr_free(XICSState *icp, int irq, int num);
void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
+void xics_create_native_icp_node(XICSState *s, void *fdt,
+ uint32_t base, uint32_t count);
+
/* Internal XICS interfaces */
int get_cpu_index_by_dt_id(int cpu_dt_id);
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
` (9 preceding siblings ...)
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass Nikunj A Dadhania
@ 2016-06-23 17:47 ` Nikunj A Dadhania
2016-06-27 4:48 ` David Gibson
10 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-23 17:47 UTC (permalink / raw)
To: qemu-ppc, david; +Cc: qemu-devel, clg, nikunj, Benjamin Herrenschmidt
From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Useful to debug interrupt problems.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
hmp-commands-info.hx | 2 ++
hw/intc/xics.c | 38 ++++++++++++++++++++++++++++++++++++++
hw/ppc/ppc.c | 14 ++++++++++++++
include/hw/ppc/ppc.h | 1 +
include/hw/ppc/xics.h | 2 ++
monitor.c | 4 ++++
6 files changed, 61 insertions(+)
diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
index 7da9e6c..e4b90b9 100644
--- a/hmp-commands-info.hx
+++ b/hmp-commands-info.hx
@@ -203,6 +203,8 @@ ETEXI
.mhandler.cmd = sun4m_hmp_info_pic,
#elif defined(TARGET_LM32)
.mhandler.cmd = lm32_hmp_info_pic,
+#elif defined(TARGET_PPC)
+ .mhandler.cmd = ppc_hmp_info_pic,
#else
.mhandler.cmd = hmp_info_pic,
#endif
diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index e2aa48d..19eeea9 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -35,6 +35,9 @@
#include "hw/ppc/xics.h"
#include "qemu/error-report.h"
#include "qapi/visitor.h"
+#include "monitor/monitor.h"
+
+static XICSState *g_xics;
int get_cpu_index_by_dt_id(int cpu_dt_id)
{
@@ -192,6 +195,9 @@ static void xics_common_initfn(Object *obj)
object_property_add(obj, "nr_servers", "int",
xics_prop_get_nr_servers, xics_prop_set_nr_servers,
NULL, NULL, NULL);
+
+ /* For exclusive use of monitor command */
+ g_xics = XICS_COMMON(obj);
}
static void xics_common_class_init(ObjectClass *oc, void *data)
@@ -636,6 +642,38 @@ static int ics_dispatch_post_load(void *opaque, int version_id)
return 0;
}
+void xics_hmp_info_pic(Monitor *mon, const QDict *qdict)
+{
+ ICSState *ics;
+ uint32_t i;
+
+ for (i = 0; i < g_xics->nr_servers; i++) {
+ ICPState *icp = &g_xics->ss[i];
+
+ if (!icp->output) {
+ continue;
+ }
+ monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
+ i, icp->xirr, icp->xirr_owner,
+ icp->pending_priority, icp->mfrr);
+ }
+ QLIST_FOREACH(ics, &g_xics->ics, list) {
+ monitor_printf(mon, "ICS %4x..%4x %p\n",
+ ics->offset, ics->offset + ics->nr_irqs - 1, ics);
+ for (i = 0; i < ics->nr_irqs; i++) {
+ ICSIRQState *irq = ics->irqs + i;
+
+ if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
+ continue;
+ }
+ monitor_printf(mon, " %4x %s %02x %02x\n",
+ ics->offset + i,
+ (irq->flags & XICS_FLAGS_IRQ_LSI) ? "LSI" : "MSI",
+ irq->priority, irq->status);
+ }
+ }
+}
+
static const VMStateDescription vmstate_ics_irq = {
.name = "ics/irq",
.version_id = 2,
diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
index 1bcf740..f3ee1d6 100644
--- a/hw/ppc/ppc.c
+++ b/hw/ppc/ppc.c
@@ -27,6 +27,7 @@
#include "hw/hw.h"
#include "hw/ppc/ppc.h"
#include "hw/ppc/ppc_e500.h"
+#include "hw/i386/pc.h"
#include "qemu/timer.h"
#include "sysemu/sysemu.h"
#include "sysemu/cpus.h"
@@ -38,6 +39,10 @@
#include "kvm_ppc.h"
#include "trace.h"
+#if defined(TARGET_PPC64)
+#include "hw/ppc/xics.h"
+#endif
+
//#define PPC_DEBUG_IRQ
//#define PPC_DEBUG_TB
@@ -1343,3 +1348,12 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
return NULL;
}
+
+void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict)
+{
+ /* Call in turn every PIC around. OpenPIC doesn't have one yet */
+#ifdef TARGET_PPC64
+ xics_hmp_info_pic(mon, qdict);
+#endif
+ hmp_info_pic(mon, qdict);
+}
diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
index 5617dc4..8076797 100644
--- a/include/hw/ppc/ppc.h
+++ b/include/hw/ppc/ppc.h
@@ -3,6 +3,7 @@
#include "target-ppc/cpu-qom.h"
+void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict);
void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
/* PowerPC hardware exceptions management helpers */
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 0e47ecb..1dbfa2c 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -218,4 +218,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
ICSState *xics_find_source(XICSState *icp, int irq);
void xics_add_ics(XICSState *xics);
+void xics_hmp_info_pic(Monitor *mon, const QDict *qdict);
+
#endif /* __XICS_H__ */
diff --git a/monitor.c b/monitor.c
index 6f960f1..66d682b 100644
--- a/monitor.c
+++ b/monitor.c
@@ -94,6 +94,10 @@
#include "hw/s390x/storage-keys.h"
#endif
+#if defined(TARGET_PPC)
+#include "hw/ppc/ppc.h"
+#endif
+
/*
* Supported types:
*
--
2.7.4
^ permalink raw reply related [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr Nikunj A Dadhania
@ 2016-06-24 5:17 ` David Gibson
2016-06-24 5:53 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-24 5:17 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 12806 bytes --]
On Thu, Jun 23, 2016 at 11:17:20PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The common class doesn't change, the KVM one is sPAPR specific. Rename
> variables and functions to xics_spapr.
>
> Retain the type name as "xics" to preserve migration for existing sPAPR
> guests.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> hw/intc/xics.c | 29 +++++++++++++++--------------
> hw/intc/xics_kvm.c | 6 +++---
> hw/ppc/spapr.c | 7 ++++---
> hw/ppc/spapr_events.c | 2 +-
> hw/ppc/spapr_pci.c | 10 +++++-----
> hw/ppc/spapr_vio.c | 2 +-
> include/hw/ppc/xics.h | 29 +++++++++++++++++------------
> 7 files changed, 46 insertions(+), 39 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index cce7f3d..a715532 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -729,7 +729,8 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
> return -1;
> }
>
> -int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)
> +int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> + Error **errp)
> {
> ICSState *ics = &icp->ics[src];
> int irq;
> @@ -760,8 +761,8 @@ int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp)
> * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
> * If align==true, aligns the first IRQ number to num.
> */
> -int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
> - Error **errp)
> +int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
> + bool align, Error **errp)
> {
> int i, first = -1;
> ICSState *ics = &icp->ics[src];
> @@ -810,7 +811,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
> }
> }
>
> -void xics_free(XICSState *icp, int irq, int num)
> +void xics_spapr_free(XICSState *icp, int irq, int num)
> {
> int src = xics_find_source(icp, irq);
>
> @@ -1029,7 +1030,7 @@ static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
> }
> }
>
> -static void xics_realize(DeviceState *dev, Error **errp)
> +static void xics_spapr_realize(DeviceState *dev, Error **errp)
> {
> XICSState *icp = XICS(dev);
> Error *error = NULL;
> @@ -1068,7 +1069,7 @@ static void xics_realize(DeviceState *dev, Error **errp)
> }
> }
>
> -static void xics_initfn(Object *obj)
> +static void xics_spapr_initfn(Object *obj)
> {
> XICSState *xics = XICS(obj);
>
> @@ -1077,29 +1078,29 @@ static void xics_initfn(Object *obj)
> xics->ics->icp = xics;
> }
>
> -static void xics_class_init(ObjectClass *oc, void *data)
> +static void xics_spapr_class_init(ObjectClass *oc, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(oc);
> - XICSStateClass *xsc = XICS_CLASS(oc);
> + XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
>
> - dc->realize = xics_realize;
> + dc->realize = xics_spapr_realize;
> xsc->set_nr_irqs = xics_set_nr_irqs;
> xsc->set_nr_servers = xics_set_nr_servers;
> }
>
> -static const TypeInfo xics_info = {
> - .name = TYPE_XICS,
> +static const TypeInfo xics_spapr_info = {
> + .name = TYPE_XICS_SPAPR,
> .parent = TYPE_XICS_COMMON,
> .instance_size = sizeof(XICSState),
> .class_size = sizeof(XICSStateClass),
> - .class_init = xics_class_init,
> - .instance_init = xics_initfn,
> + .class_init = xics_spapr_class_init,
> + .instance_init = xics_spapr_initfn,
> };
>
> static void xics_register_types(void)
> {
> type_register_static(&xics_common_info);
> - type_register_static(&xics_info);
> + type_register_static(&xics_spapr_info);
> type_register_static(&ics_info);
> type_register_static(&icp_info);
> }
> diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
> index b17d6a9..90d657e 100644
> --- a/hw/intc/xics_kvm.c
> +++ b/hw/intc/xics_kvm.c
> @@ -495,8 +495,8 @@ static void xics_kvm_class_init(ObjectClass *oc, void *data)
> xsc->set_nr_servers = xics_kvm_set_nr_servers;
> }
>
> -static const TypeInfo xics_kvm_info = {
> - .name = TYPE_KVM_XICS,
> +static const TypeInfo xics_spapr_kvm_info = {
> + .name = TYPE_XICS_SPAPR_KVM,
> .parent = TYPE_XICS_COMMON,
> .instance_size = sizeof(KVMXICSState),
> .class_init = xics_kvm_class_init,
> @@ -505,7 +505,7 @@ static const TypeInfo xics_kvm_info = {
>
> static void xics_kvm_register_types(void)
> {
> - type_register_static(&xics_kvm_info);
> + type_register_static(&xics_spapr_kvm_info);
> type_register_static(&ics_kvm_info);
> type_register_static(&icp_kvm_info);
> }
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 0b6bb9c..a8d497c 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -122,7 +122,8 @@ static XICSState *xics_system_init(MachineState *machine,
> Error *err = NULL;
>
> if (machine_kernel_irqchip_allowed(machine)) {
> - icp = try_create_xics(TYPE_KVM_XICS, nr_servers, nr_irqs, &err);
> + icp = try_create_xics(TYPE_XICS_SPAPR_KVM, nr_servers, nr_irqs,
> + &err);
> }
> if (machine_kernel_irqchip_required(machine) && !icp) {
> error_reportf_err(err,
> @@ -133,7 +134,7 @@ static XICSState *xics_system_init(MachineState *machine,
> }
>
> if (!icp) {
> - icp = try_create_xics(TYPE_XICS, nr_servers, nr_irqs, errp);
> + icp = try_create_xics(TYPE_XICS_SPAPR, nr_servers, nr_irqs, errp);
> }
>
> return icp;
> @@ -1781,7 +1782,7 @@ static void ppc_spapr_init(MachineState *machine)
> /* Set up Interrupt Controller before we create the VCPUs */
> spapr->icp = xics_system_init(machine,
> DIV_ROUND_UP(max_cpus * smt, smp_threads),
> - XICS_IRQS, &error_fatal);
> + XICS_IRQS_SPAPR, &error_fatal);
>
> if (smc->dr_lmb_enabled) {
> spapr_validate_node_memory(machine, &error_fatal);
> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
> index af80992..0585f8a 100644
> --- a/hw/ppc/spapr_events.c
> +++ b/hw/ppc/spapr_events.c
> @@ -603,7 +603,7 @@ out_no_events:
> void spapr_events_init(sPAPRMachineState *spapr)
> {
> QTAILQ_INIT(&spapr->pending_events);
> - spapr->check_exception_irq = xics_alloc(spapr->icp, 0, 0, false,
> + spapr->check_exception_irq = xics_spapr_alloc(spapr->icp, 0, 0, false,
> &error_fatal);
> spapr->epow_notifier.notify = spapr_powerdown_req;
> qemu_register_powerdown_notifier(&spapr->epow_notifier);
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 9f28fb3..451651d 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -322,7 +322,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> return;
> }
>
> - xics_free(spapr->icp, msi->first_irq, msi->num);
> + xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
> if (msi_present(pdev)) {
> spapr_msi_setmsg(pdev, 0, false, 0, 0);
> }
> @@ -360,7 +360,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> }
>
> /* Allocate MSIs */
> - irq = xics_alloc_block(spapr->icp, 0, req_num, false,
> + irq = xics_spapr_alloc_block(spapr->icp, 0, req_num, false,
> ret_intr_type == RTAS_TYPE_MSI, &err);
> if (err) {
> error_reportf_err(err, "Can't allocate MSIs for device %x: ",
> @@ -371,7 +371,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>
> /* Release previous MSIs */
> if (msi) {
> - xics_free(spapr->icp, msi->first_irq, msi->num);
> + xics_spapr_free(spapr->icp, msi->first_irq, msi->num);
> g_hash_table_remove(phb->msi, &config_addr);
> }
>
> @@ -1442,7 +1442,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
> uint32_t irq;
> Error *local_err = NULL;
>
> - irq = xics_alloc_block(spapr->icp, 0, 1, true, false, &local_err);
> + irq = xics_spapr_alloc_block(spapr->icp, 0, 1, true, false, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> error_prepend(errp, "can't allocate LSIs: ");
> @@ -1801,7 +1801,7 @@ int spapr_populate_pci_dt(sPAPRPHBState *phb,
> _FDT(fdt_setprop(fdt, bus_off, "ranges", &ranges, sizeof_ranges));
> _FDT(fdt_setprop(fdt, bus_off, "reg", &bus_reg, sizeof(bus_reg)));
> _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pci-config-space-type", 0x1));
> - _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS));
> + _FDT(fdt_setprop_cell(fdt, bus_off, "ibm,pe-total-#msi", XICS_IRQS_SPAPR));
>
> /* Build the interrupt-map, this must matches what is done
> * in pci_spapr_map_irq
> diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
> index ae40db8..7ffd23e 100644
> --- a/hw/ppc/spapr_vio.c
> +++ b/hw/ppc/spapr_vio.c
> @@ -463,7 +463,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
> dev->qdev.id = id;
> }
>
> - dev->irq = xics_alloc(spapr->icp, 0, dev->irq, false, &local_err);
> + dev->irq = xics_spapr_alloc(spapr->icp, 0, dev->irq, false, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> return;
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 9091054..452a978 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -32,20 +32,24 @@
> #define TYPE_XICS_COMMON "xics-common"
> #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
>
> -#define TYPE_XICS "xics"
> -#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
> +/*
> + * Retain xics as the type name to be compatible for migration. Rest all the
> + * functions, class and variables are renamed as xics_spapr.
> + */
> +#define TYPE_XICS_SPAPR "xics"
> +#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
This should change to XICS_SPAPR to match the TYPE macro.
>
> -#define TYPE_KVM_XICS "xics-kvm"
> -#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS)
> +#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
> +#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
Likewise XICS_SPAPR_KVM().
> #define XICS_COMMON_CLASS(klass) \
> OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
> -#define XICS_CLASS(klass) \
> - OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS)
> +#define XICS_SPAPR_CLASS(klass) \
> + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_SPAPR)
> #define XICS_COMMON_GET_CLASS(obj) \
> OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
> -#define XICS_GET_CLASS(obj) \
> - OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS)
> +#define XICS_SPAPR_GET_CLASS(obj) \
> + OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
>
> #define XICS_IPI 0x2
> #define XICS_BUID 0x1
> @@ -157,14 +161,15 @@ struct ICSIRQState {
> uint8_t flags;
> };
>
> -#define XICS_IRQS 1024
> +#define XICS_IRQS_SPAPR 1024
>
> qemu_irq xics_get_qirq(XICSState *icp, int irq);
> void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
> -int xics_alloc(XICSState *icp, int src, int irq_hint, bool lsi, Error **errp);
> -int xics_alloc_block(XICSState *icp, int src, int num, bool lsi, bool align,
> +int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> Error **errp);
> -void xics_free(XICSState *icp, int irq, int num);
> +int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
> + bool align, Error **errp);
> +void xics_spapr_free(XICSState *icp, int irq, int num);
>
> void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
> void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file Nikunj A Dadhania
@ 2016-06-24 5:19 ` David Gibson
2016-06-24 5:57 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-24 5:19 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 33595 bytes --]
On Thu, Jun 23, 2016 at 11:17:21PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Leave the core ICP/ICS logic in xics.c and move the top level
> class wrapper, hypercall and RTAS handlers to xics_spapr.c
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to
> xics_spapr.c]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> default-configs/ppc64-softmmu.mak | 1 +
> hw/intc/Makefile.objs | 1 +
> hw/intc/xics.c | 418 +-----------------------------------
> hw/intc/xics_spapr.c | 432 ++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/xics.h | 21 ++
> 5 files changed, 464 insertions(+), 409 deletions(-)
> create mode 100644 hw/intc/xics_spapr.c
>
> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
> index bb71b23..c4be59f 100644
> --- a/default-configs/ppc64-softmmu.mak
> +++ b/default-configs/ppc64-softmmu.mak
> @@ -49,6 +49,7 @@ CONFIG_ETSEC=y
> CONFIG_LIBDECNUMBER=y
> # For pSeries
> CONFIG_XICS=$(CONFIG_PSERIES)
> +CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
> # For PReP
> CONFIG_MC146818RTC=y
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index c7bbf88..530df2e 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
> obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
> obj-$(CONFIG_SH4) += sh_intc.o
> obj-$(CONFIG_XICS) += xics.o
> +obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
> obj-$(CONFIG_S390_FLIC) += s390_flic.o
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index a715532..6ca391f 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -32,12 +32,11 @@
> #include "hw/hw.h"
> #include "trace.h"
> #include "qemu/timer.h"
> -#include "hw/ppc/spapr.h"
> #include "hw/ppc/xics.h"
> #include "qemu/error-report.h"
> #include "qapi/visitor.h"
>
> -static int get_cpu_index_by_dt_id(int cpu_dt_id)
> +int get_cpu_index_by_dt_id(int cpu_dt_id)
If this is made public it needs xics_*() name the current one is too
generic for a global symbol.
> {
> PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
>
> @@ -242,7 +241,7 @@ static void icp_resend(XICSState *icp, int server)
> ics_resend(icp->ics);
> }
>
> -static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> {
> ICPState *ss = icp->ss + server;
> uint8_t old_cppr;
> @@ -266,7 +265,7 @@ static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> }
> }
>
> -static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> {
> ICPState *ss = icp->ss + server;
>
> @@ -276,7 +275,7 @@ static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> }
> }
>
> -static uint32_t icp_accept(ICPState *ss)
> +uint32_t icp_accept(ICPState *ss)
> {
> uint32_t xirr = ss->xirr;
>
> @@ -289,7 +288,7 @@ static uint32_t icp_accept(ICPState *ss)
> return xirr;
> }
>
> -static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
> +void icp_eoi(XICSState *icp, int server, uint32_t xirr)
> {
> ICPState *ss = icp->ss + server;
>
> @@ -390,12 +389,6 @@ static const TypeInfo icp_info = {
> /*
> * ICS: Source layer
> */
> -static int ics_valid_irq(ICSState *ics, uint32_t nr)
> -{
> - return (nr >= ics->offset)
> - && (nr < (ics->offset + ics->nr_irqs));
> -}
> -
> static void resend_msi(ICSState *ics, int srcno)
> {
> ICSIRQState *irq = ics->irqs + srcno;
> @@ -480,8 +473,8 @@ static void write_xive_lsi(ICSState *ics, int srcno)
> resend_lsi(ics, srcno);
> }
>
> -static void ics_write_xive(ICSState *ics, int nr, int server,
> - uint8_t priority, uint8_t saved_priority)
> +void ics_write_xive(ICSState *ics, int nr, int server,
> + uint8_t priority, uint8_t saved_priority)
> {
> int srcno = nr - ics->offset;
> ICSIRQState *irq = ics->irqs + srcno;
> @@ -658,7 +651,7 @@ static const TypeInfo ics_info = {
> /*
> * Exported functions
> */
> -static int xics_find_source(XICSState *icp, int irq)
> +int xics_find_source(XICSState *icp, int irq)
> {
> int sources = 1;
> int src;
> @@ -686,7 +679,7 @@ qemu_irq xics_get_qirq(XICSState *icp, int irq)
> return NULL;
> }
>
> -static void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
> +void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
> {
> assert(!(ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MASK));
>
> @@ -705,402 +698,9 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
> ics_set_irq_type(ics, irq - ics->offset, lsi);
> }
>
> -#define ICS_IRQ_FREE(ics, srcno) \
> - (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
> -
> -static int ics_find_free_block(ICSState *ics, int num, int alignnum)
> -{
> - int first, i;
> -
> - for (first = 0; first < ics->nr_irqs; first += alignnum) {
> - if (num > (ics->nr_irqs - first)) {
> - return -1;
> - }
> - for (i = first; i < first + num; ++i) {
> - if (!ICS_IRQ_FREE(ics, i)) {
> - break;
> - }
> - }
> - if (i == (first + num)) {
> - return first;
> - }
> - }
> -
> - return -1;
> -}
> -
> -int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> - Error **errp)
> -{
> - ICSState *ics = &icp->ics[src];
> - int irq;
> -
> - if (irq_hint) {
> - assert(src == xics_find_source(icp, irq_hint));
> - if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
> - error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
> - return -1;
> - }
> - irq = irq_hint;
> - } else {
> - irq = ics_find_free_block(ics, 1, 1);
> - if (irq < 0) {
> - error_setg(errp, "can't allocate IRQ: no IRQ left");
> - return -1;
> - }
> - irq += ics->offset;
> - }
> -
> - ics_set_irq_type(ics, irq - ics->offset, lsi);
> - trace_xics_alloc(src, irq);
> -
> - return irq;
> -}
> -
> -/*
> - * Allocate block of consecutive IRQs, and return the number of the first IRQ in the block.
> - * If align==true, aligns the first IRQ number to num.
> - */
> -int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
> - bool align, Error **errp)
> -{
> - int i, first = -1;
> - ICSState *ics = &icp->ics[src];
> -
> - assert(src == 0);
> - /*
> - * MSIMesage::data is used for storing VIRQ so
> - * it has to be aligned to num to support multiple
> - * MSI vectors. MSI-X is not affected by this.
> - * The hint is used for the first IRQ, the rest should
> - * be allocated continuously.
> - */
> - if (align) {
> - assert((num == 1) || (num == 2) || (num == 4) ||
> - (num == 8) || (num == 16) || (num == 32));
> - first = ics_find_free_block(ics, num, num);
> - } else {
> - first = ics_find_free_block(ics, num, 1);
> - }
> - if (first < 0) {
> - error_setg(errp, "can't find a free %d-IRQ block", num);
> - return -1;
> - }
> -
> - if (first >= 0) {
> - for (i = first; i < first + num; ++i) {
> - ics_set_irq_type(ics, i, lsi);
> - }
> - }
> - first += ics->offset;
> -
> - trace_xics_alloc_block(src, first, num, lsi, align);
> -
> - return first;
> -}
> -
> -static void ics_free(ICSState *ics, int srcno, int num)
> -{
> - int i;
> -
> - for (i = srcno; i < srcno + num; ++i) {
> - if (ICS_IRQ_FREE(ics, i)) {
> - trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
> - }
> - memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
> - }
> -}
> -
> -void xics_spapr_free(XICSState *icp, int irq, int num)
> -{
> - int src = xics_find_source(icp, irq);
> -
> - if (src >= 0) {
> - ICSState *ics = &icp->ics[src];
> -
> - /* FIXME: implement multiple sources */
> - assert(src == 0);
> -
> - trace_xics_ics_free(ics - icp->ics, irq, num);
> - ics_free(ics, irq - ics->offset, num);
> - }
> -}
> -
> -/*
> - * Guest interfaces
> - */
> -
> -static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUState *cs = CPU(cpu);
> - target_ulong cppr = args[0];
> -
> - icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - target_ulong server = get_cpu_index_by_dt_id(args[0]);
> - target_ulong mfrr = args[1];
> -
> - if (server >= spapr->icp->nr_servers) {
> - return H_PARAMETER;
> - }
> -
> - icp_set_mfrr(spapr->icp, server, mfrr);
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUState *cs = CPU(cpu);
> - uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
> -
> - args[0] = xirr;
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUState *cs = CPU(cpu);
> - ICPState *ss = &spapr->icp->ss[cs->cpu_index];
> - uint32_t xirr = icp_accept(ss);
> -
> - args[0] = xirr;
> - args[1] = cpu_get_host_ticks();
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUState *cs = CPU(cpu);
> - target_ulong xirr = args[0];
> -
> - icp_eoi(spapr->icp, cs->cpu_index, xirr);
> - return H_SUCCESS;
> -}
> -
> -static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - target_ulong opcode, target_ulong *args)
> -{
> - CPUState *cs = CPU(cpu);
> - ICPState *ss = &spapr->icp->ss[cs->cpu_index];
> -
> - args[0] = ss->xirr;
> - args[1] = ss->mfrr;
> -
> - return H_SUCCESS;
> -}
> -
> -static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - uint32_t token,
> - uint32_t nargs, target_ulong args,
> - uint32_t nret, target_ulong rets)
> -{
> - ICSState *ics = spapr->icp->ics;
> - uint32_t nr, server, priority;
> -
> - if ((nargs != 3) || (nret != 1)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - nr = rtas_ld(args, 0);
> - server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
> - priority = rtas_ld(args, 2);
> -
> - if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
> - || (priority > 0xff)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - ics_write_xive(ics, nr, server, priority, priority);
> -
> - rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> -}
> -
> -static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - uint32_t token,
> - uint32_t nargs, target_ulong args,
> - uint32_t nret, target_ulong rets)
> -{
> - ICSState *ics = spapr->icp->ics;
> - uint32_t nr;
> -
> - if ((nargs != 1) || (nret != 3)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - nr = rtas_ld(args, 0);
> -
> - if (!ics_valid_irq(ics, nr)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> - rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
> - rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
> -}
> -
> -static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - uint32_t token,
> - uint32_t nargs, target_ulong args,
> - uint32_t nret, target_ulong rets)
> -{
> - ICSState *ics = spapr->icp->ics;
> - uint32_t nr;
> -
> - if ((nargs != 1) || (nret != 1)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - nr = rtas_ld(args, 0);
> -
> - if (!ics_valid_irq(ics, nr)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
> - ics->irqs[nr - ics->offset].priority);
> -
> - rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> -}
> -
> -static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> - uint32_t token,
> - uint32_t nargs, target_ulong args,
> - uint32_t nret, target_ulong rets)
> -{
> - ICSState *ics = spapr->icp->ics;
> - uint32_t nr;
> -
> - if ((nargs != 1) || (nret != 1)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - nr = rtas_ld(args, 0);
> -
> - if (!ics_valid_irq(ics, nr)) {
> - rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> - return;
> - }
> -
> - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
> - ics->irqs[nr - ics->offset].saved_priority,
> - ics->irqs[nr - ics->offset].saved_priority);
> -
> - rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> -}
> -
> -/*
> - * XICS
> - */
> -
> -static void xics_set_nr_irqs(XICSState *icp, uint32_t nr_irqs, Error **errp)
> -{
> - icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
> -}
> -
> -static void xics_set_nr_servers(XICSState *icp, uint32_t nr_servers,
> - Error **errp)
> -{
> - int i;
> -
> - icp->nr_servers = nr_servers;
> -
> - icp->ss = g_malloc0(icp->nr_servers*sizeof(ICPState));
> - for (i = 0; i < icp->nr_servers; i++) {
> - char buffer[32];
> - object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
> - snprintf(buffer, sizeof(buffer), "icp[%d]", i);
> - object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
> - errp);
> - }
> -}
> -
> -static void xics_spapr_realize(DeviceState *dev, Error **errp)
> -{
> - XICSState *icp = XICS(dev);
> - Error *error = NULL;
> - int i;
> -
> - if (!icp->nr_servers) {
> - error_setg(errp, "Number of servers needs to be greater 0");
> - return;
> - }
> -
> - /* Registration of global state belongs into realize */
> - spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
> - spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
> - spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
> - spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
> -
> - spapr_register_hypercall(H_CPPR, h_cppr);
> - spapr_register_hypercall(H_IPI, h_ipi);
> - spapr_register_hypercall(H_XIRR, h_xirr);
> - spapr_register_hypercall(H_XIRR_X, h_xirr_x);
> - spapr_register_hypercall(H_EOI, h_eoi);
> - spapr_register_hypercall(H_IPOLL, h_ipoll);
> -
> - object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
> - if (error) {
> - error_propagate(errp, error);
> - return;
> - }
> -
> - for (i = 0; i < icp->nr_servers; i++) {
> - object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
> - if (error) {
> - error_propagate(errp, error);
> - return;
> - }
> - }
> -}
> -
> -static void xics_spapr_initfn(Object *obj)
> -{
> - XICSState *xics = XICS(obj);
> -
> - xics->ics = ICS(object_new(TYPE_ICS));
> - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
> - xics->ics->icp = xics;
> -}
> -
> -static void xics_spapr_class_init(ObjectClass *oc, void *data)
> -{
> - DeviceClass *dc = DEVICE_CLASS(oc);
> - XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
> -
> - dc->realize = xics_spapr_realize;
> - xsc->set_nr_irqs = xics_set_nr_irqs;
> - xsc->set_nr_servers = xics_set_nr_servers;
> -}
> -
> -static const TypeInfo xics_spapr_info = {
> - .name = TYPE_XICS_SPAPR,
> - .parent = TYPE_XICS_COMMON,
> - .instance_size = sizeof(XICSState),
> - .class_size = sizeof(XICSStateClass),
> - .class_init = xics_spapr_class_init,
> - .instance_init = xics_spapr_initfn,
> -};
> -
> static void xics_register_types(void)
> {
> type_register_static(&xics_common_info);
> - type_register_static(&xics_spapr_info);
> type_register_static(&ics_info);
> type_register_static(&icp_info);
> }
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> new file mode 100644
> index 0000000..48d458a
> --- /dev/null
> +++ b/hw/intc/xics_spapr.c
> @@ -0,0 +1,432 @@
> +/*
> + * QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
> + *
> + * PAPR Virtualized Interrupt System, aka ICS/ICP aka xics
> + *
> + * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "cpu.h"
> +#include "hw/hw.h"
> +#include "trace.h"
> +#include "qemu/timer.h"
> +#include "hw/ppc/spapr.h"
> +#include "hw/ppc/xics.h"
> +#include "qapi/visitor.h"
> +#include "qapi/error.h"
> +
> +/*
> + * Guest interfaces
> + */
> +
> +static target_ulong h_cppr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUState *cs = CPU(cpu);
> + target_ulong cppr = args[0];
> +
> + icp_set_cppr(spapr->icp, cs->cpu_index, cppr);
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_ipi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + target_ulong server = get_cpu_index_by_dt_id(args[0]);
> + target_ulong mfrr = args[1];
> +
> + if (server >= spapr->icp->nr_servers) {
> + return H_PARAMETER;
> + }
> +
> + icp_set_mfrr(spapr->icp, server, mfrr);
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUState *cs = CPU(cpu);
> + uint32_t xirr = icp_accept(spapr->icp->ss + cs->cpu_index);
> +
> + args[0] = xirr;
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUState *cs = CPU(cpu);
> + ICPState *ss = &spapr->icp->ss[cs->cpu_index];
> + uint32_t xirr = icp_accept(ss);
> +
> + args[0] = xirr;
> + args[1] = cpu_get_host_ticks();
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_eoi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUState *cs = CPU(cpu);
> + target_ulong xirr = args[0];
> +
> + icp_eoi(spapr->icp, cs->cpu_index, xirr);
> + return H_SUCCESS;
> +}
> +
> +static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + target_ulong opcode, target_ulong *args)
> +{
> + CPUState *cs = CPU(cpu);
> + ICPState *ss = &spapr->icp->ss[cs->cpu_index];
> +
> + args[0] = ss->xirr;
> + args[1] = ss->mfrr;
> +
> + return H_SUCCESS;
> +}
> +
> +static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + uint32_t token,
> + uint32_t nargs, target_ulong args,
> + uint32_t nret, target_ulong rets)
> +{
> + ICSState *ics = spapr->icp->ics;
> + uint32_t nr, server, priority;
> +
> + if ((nargs != 3) || (nret != 1)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + nr = rtas_ld(args, 0);
> + server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
> + priority = rtas_ld(args, 2);
> +
> + if (!ics_valid_irq(ics, nr) || (server >= ics->icp->nr_servers)
> + || (priority > 0xff)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + ics_write_xive(ics, nr, server, priority, priority);
> +
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> +}
> +
> +static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + uint32_t token,
> + uint32_t nargs, target_ulong args,
> + uint32_t nret, target_ulong rets)
> +{
> + ICSState *ics = spapr->icp->ics;
> + uint32_t nr;
> +
> + if ((nargs != 1) || (nret != 3)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + nr = rtas_ld(args, 0);
> +
> + if (!ics_valid_irq(ics, nr)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> + rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
> + rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
> +}
> +
> +static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + uint32_t token,
> + uint32_t nargs, target_ulong args,
> + uint32_t nret, target_ulong rets)
> +{
> + ICSState *ics = spapr->icp->ics;
> + uint32_t nr;
> +
> + if ((nargs != 1) || (nret != 1)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + nr = rtas_ld(args, 0);
> +
> + if (!ics_valid_irq(ics, nr)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
> + ics->irqs[nr - ics->offset].priority);
> +
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> +}
> +
> +static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> + uint32_t token,
> + uint32_t nargs, target_ulong args,
> + uint32_t nret, target_ulong rets)
> +{
> + ICSState *ics = spapr->icp->ics;
> + uint32_t nr;
> +
> + if ((nargs != 1) || (nret != 1)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + nr = rtas_ld(args, 0);
> +
> + if (!ics_valid_irq(ics, nr)) {
> + rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> + return;
> + }
> +
> + ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
> + ics->irqs[nr - ics->offset].saved_priority,
> + ics->irqs[nr - ics->offset].saved_priority);
> +
> + rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> +}
> +
> +static void xics_spapr_set_nr_irqs(XICSState *icp, uint32_t nr_irqs,
> + Error **errp)
> +{
> + icp->nr_irqs = icp->ics->nr_irqs = nr_irqs;
> +}
> +
> +static void xics_spapr_set_nr_servers(XICSState *icp, uint32_t nr_servers,
> + Error **errp)
> +{
> + int i;
> +
> + icp->nr_servers = nr_servers;
> +
> + icp->ss = g_malloc0(icp->nr_servers * sizeof(ICPState));
> + for (i = 0; i < icp->nr_servers; i++) {
> + char buffer[32];
> + object_initialize(&icp->ss[i], sizeof(icp->ss[i]), TYPE_ICP);
> + snprintf(buffer, sizeof(buffer), "icp[%d]", i);
> + object_property_add_child(OBJECT(icp), buffer, OBJECT(&icp->ss[i]),
> + errp);
> + }
> +}
> +
> +static void xics_spapr_realize(DeviceState *dev, Error **errp)
> +{
> + XICSState *icp = XICS(dev);
> + Error *error = NULL;
> + int i;
> +
> + if (!icp->nr_servers) {
> + error_setg(errp, "Number of servers needs to be greater 0");
> + return;
> + }
> +
> + /* Registration of global state belongs into realize */
> + spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_set_xive);
> + spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_get_xive);
> + spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_int_off);
> + spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_int_on);
> +
> + spapr_register_hypercall(H_CPPR, h_cppr);
> + spapr_register_hypercall(H_IPI, h_ipi);
> + spapr_register_hypercall(H_XIRR, h_xirr);
> + spapr_register_hypercall(H_XIRR_X, h_xirr_x);
> + spapr_register_hypercall(H_EOI, h_eoi);
> + spapr_register_hypercall(H_IPOLL, h_ipoll);
> +
> + object_property_set_bool(OBJECT(icp->ics), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> +
> + for (i = 0; i < icp->nr_servers; i++) {
> + object_property_set_bool(OBJECT(&icp->ss[i]), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> + }
> +}
> +
> +static void xics_spapr_initfn(Object *obj)
> +{
> + XICSState *xics = XICS(obj);
> +
> + xics->ics = ICS(object_new(TYPE_ICS));
> + object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
> + xics->ics->icp = xics;
> +}
> +
> +static void xics_spapr_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + XICSStateClass *xsc = XICS_SPAPR_CLASS(oc);
> +
> + dc->realize = xics_spapr_realize;
> + xsc->set_nr_irqs = xics_spapr_set_nr_irqs;
> + xsc->set_nr_servers = xics_spapr_set_nr_servers;
> +}
> +
> +static const TypeInfo xics_spapr_info = {
> + .name = TYPE_XICS_SPAPR,
> + .parent = TYPE_XICS_COMMON,
> + .instance_size = sizeof(XICSState),
> + .class_size = sizeof(XICSStateClass),
> + .class_init = xics_spapr_class_init,
> + .instance_init = xics_spapr_initfn,
> +};
> +
> +#define ICS_IRQ_FREE(ics, srcno) \
> + (!((ics)->irqs[(srcno)].flags & (XICS_FLAGS_IRQ_MASK)))
> +
> +static int ics_find_free_block(ICSState *ics, int num, int alignnum)
> +{
> + int first, i;
> +
> + for (first = 0; first < ics->nr_irqs; first += alignnum) {
> + if (num > (ics->nr_irqs - first)) {
> + return -1;
> + }
> + for (i = first; i < first + num; ++i) {
> + if (!ICS_IRQ_FREE(ics, i)) {
> + break;
> + }
> + }
> + if (i == (first + num)) {
> + return first;
> + }
> + }
> +
> + return -1;
> +}
> +
> +int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> + Error **errp)
> +{
> + ICSState *ics = &icp->ics[src];
> + int irq;
> +
> + if (irq_hint) {
> + assert(src == xics_find_source(icp, irq_hint));
> + if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
> + error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
> + return -1;
> + }
> + irq = irq_hint;
> + } else {
> + irq = ics_find_free_block(ics, 1, 1);
> + if (irq < 0) {
> + error_setg(errp, "can't allocate IRQ: no IRQ left");
> + return -1;
> + }
> + irq += ics->offset;
> + }
> +
> + ics_set_irq_type(ics, irq - ics->offset, lsi);
> + trace_xics_alloc(src, irq);
> +
> + return irq;
> +}
> +
> +/*
> + * Allocate block of consecutive IRQs, and return the number of the first IRQ in
> + * the block. If align==true, aligns the first IRQ number to num.
> + */
> +int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
> + bool align, Error **errp)
> +{
> + int i, first = -1;
> + ICSState *ics = &icp->ics[src];
> +
> + assert(src == 0);
> + /*
> + * MSIMesage::data is used for storing VIRQ so
> + * it has to be aligned to num to support multiple
> + * MSI vectors. MSI-X is not affected by this.
> + * The hint is used for the first IRQ, the rest should
> + * be allocated continuously.
> + */
> + if (align) {
> + assert((num == 1) || (num == 2) || (num == 4) ||
> + (num == 8) || (num == 16) || (num == 32));
> + first = ics_find_free_block(ics, num, num);
> + } else {
> + first = ics_find_free_block(ics, num, 1);
> + }
> + if (first < 0) {
> + error_setg(errp, "can't find a free %d-IRQ block", num);
> + return -1;
> + }
> +
> + if (first >= 0) {
> + for (i = first; i < first + num; ++i) {
> + ics_set_irq_type(ics, i, lsi);
> + }
> + }
> + first += ics->offset;
> +
> + trace_xics_alloc_block(src, first, num, lsi, align);
> +
> + return first;
> +}
> +
> +static void ics_free(ICSState *ics, int srcno, int num)
> +{
> + int i;
> +
> + for (i = srcno; i < srcno + num; ++i) {
> + if (ICS_IRQ_FREE(ics, i)) {
> + trace_xics_ics_free_warn(ics - ics->icp->ics, i + ics->offset);
> + }
> + memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
> + }
> +}
> +
> +void xics_spapr_free(XICSState *icp, int irq, int num)
> +{
> + int src = xics_find_source(icp, irq);
> +
> + if (src >= 0) {
> + ICSState *ics = &icp->ics[src];
> +
> + /* FIXME: implement multiple sources */
> + assert(src == 0);
> +
> + trace_xics_ics_free(ics - icp->ics, irq, num);
> + ics_free(ics, irq - ics->offset, num);
> + }
> +}
> +
> +static void xics_spapr_register_types(void)
> +{
> + type_register_static(&xics_spapr_info);
> +}
> +
> +type_init(xics_spapr_register_types)
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 452a978..76b45ef 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -145,6 +145,12 @@ struct ICSState {
> XICSState *icp;
> };
>
> +static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
> +{
> + return (nr >= ics->offset)
> + && (nr < (ics->offset + ics->nr_irqs));
> +}
> +
> struct ICSIRQState {
> uint32_t server;
> uint8_t priority;
> @@ -174,4 +180,19 @@ void xics_spapr_free(XICSState *icp, int irq, int num);
> void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
> void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
>
> +/* Internal XICS interfaces */
> +int get_cpu_index_by_dt_id(int cpu_dt_id);
> +
> +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
> +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
> +uint32_t icp_accept(ICPState *ss);
> +void icp_eoi(XICSState *icp, int server, uint32_t xirr);
> +
> +void ics_write_xive(ICSState *ics, int nr, int server,
> + uint8_t priority, uint8_t saved_priority);
> +
> +void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
> +
> +int xics_find_source(XICSState *icp, int irq);
> +
> #endif /* __XICS_H__ */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor Nikunj A Dadhania
@ 2016-06-24 5:21 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-24 5:21 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 2613 bytes --]
On Thu, Jun 23, 2016 at 11:17:22PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> None of the other presenter functions directly mucks with the
> internal state, so don't do it there either.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Modulo changes that will be necessary to account for review comments
on earlier patches.
> ---
> hw/intc/xics.c | 8 ++++++++
> hw/intc/xics_spapr.c | 7 ++++---
> include/hw/ppc/xics.h | 1 +
> 3 files changed, 13 insertions(+), 3 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 6ca391f..40969ee 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -288,6 +288,14 @@ uint32_t icp_accept(ICPState *ss)
> return xirr;
> }
>
> +uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
> +{
> + if (mfrr) {
> + *mfrr = ss->mfrr;
> + }
> + return ss->xirr;
> +}
> +
> void icp_eoi(XICSState *icp, int server, uint32_t xirr)
> {
> ICPState *ss = icp->ss + server;
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index 48d458a..4d5adda 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -99,10 +99,11 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> target_ulong opcode, target_ulong *args)
> {
> CPUState *cs = CPU(cpu);
> - ICPState *ss = &spapr->icp->ss[cs->cpu_index];
> + uint32_t mfrr;
> + uint32_t xirr = icp_ipoll(spapr->icp->ss + cs->cpu_index, &mfrr);
>
> - args[0] = ss->xirr;
> - args[1] = ss->mfrr;
> + args[0] = xirr;
> + args[1] = mfrr;
>
> return H_SUCCESS;
> }
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 76b45ef..32ea706 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -186,6 +186,7 @@ int get_cpu_index_by_dt_id(int cpu_dt_id);
> void icp_set_cppr(XICSState *icp, int server, uint8_t cppr);
> void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr);
> uint32_t icp_accept(ICPState *ss);
> +uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
> void icp_eoi(XICSState *icp, int server, uint32_t xirr);
>
> void ics_write_xive(ICSState *ics, int nr, int server,
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type()
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type() Nikunj A Dadhania
@ 2016-06-24 5:45 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-24 5:45 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 1956 bytes --]
On Thu, Jun 23, 2016 at 11:17:23PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
This stands on its own so I've applied it to ppc-for-2.7 (adjusting
for context conflicts, obviously).
> ---
> hw/intc/xics.c | 11 -----------
> include/hw/ppc/xics.h | 1 -
> 2 files changed, 12 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 40969ee..4f15a2d 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -695,17 +695,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi)
> lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI;
> }
>
> -void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
> -{
> - int src = xics_find_source(icp, irq);
> - ICSState *ics;
> -
> - assert(src >= 0);
> -
> - ics = &icp->ics[src];
> - ics_set_irq_type(ics, irq - ics->offset, lsi);
> -}
> -
> static void xics_register_types(void)
> {
> type_register_static(&xics_common_info);
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 32ea706..2a9b91d 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -170,7 +170,6 @@ struct ICSIRQState {
> #define XICS_IRQS_SPAPR 1024
>
> qemu_irq xics_get_qirq(XICSState *icp, int irq);
> -void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
> int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> Error **errp);
> int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr
2016-06-24 5:17 ` David Gibson
@ 2016-06-24 5:53 ` Nikunj A Dadhania
0 siblings, 0 replies; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-24 5:53 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
>> index 9091054..452a978 100644
>> --- a/include/hw/ppc/xics.h
>> +++ b/include/hw/ppc/xics.h
>> @@ -32,20 +32,24 @@
>> #define TYPE_XICS_COMMON "xics-common"
>> #define XICS_COMMON(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_COMMON)
>>
>> -#define TYPE_XICS "xics"
>> -#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS)
>> +/*
>> + * Retain xics as the type name to be compatible for migration. Rest all the
>> + * functions, class and variables are renamed as xics_spapr.
>> + */
>> +#define TYPE_XICS_SPAPR "xics"
>> +#define XICS(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_SPAPR)
>
> This should change to XICS_SPAPR to match the TYPE macro.
Done.
>
>>
>> -#define TYPE_KVM_XICS "xics-kvm"
>> -#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_KVM_XICS)
>> +#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
>> +#define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
>
> Likewise XICS_SPAPR_KVM().
>
Done.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file
2016-06-24 5:19 ` David Gibson
@ 2016-06-24 5:57 ` Nikunj A Dadhania
2016-06-24 6:12 ` David Gibson
0 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-24 5:57 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Thu, Jun 23, 2016 at 11:17:21PM +0530, Nikunj A Dadhania wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Leave the core ICP/ICS logic in xics.c and move the top level
>> class wrapper, hypercall and RTAS handlers to xics_spapr.c
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to
>> xics_spapr.c]
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> default-configs/ppc64-softmmu.mak | 1 +
>> hw/intc/Makefile.objs | 1 +
>> hw/intc/xics.c | 418 +-----------------------------------
>> hw/intc/xics_spapr.c | 432 ++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/xics.h | 21 ++
>> 5 files changed, 464 insertions(+), 409 deletions(-)
>> create mode 100644 hw/intc/xics_spapr.c
>>
>> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
>> index bb71b23..c4be59f 100644
>> --- a/default-configs/ppc64-softmmu.mak
>> +++ b/default-configs/ppc64-softmmu.mak
>> @@ -49,6 +49,7 @@ CONFIG_ETSEC=y
>> CONFIG_LIBDECNUMBER=y
>> # For pSeries
>> CONFIG_XICS=$(CONFIG_PSERIES)
>> +CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
>> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
>> # For PReP
>> CONFIG_MC146818RTC=y
>> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
>> index c7bbf88..530df2e 100644
>> --- a/hw/intc/Makefile.objs
>> +++ b/hw/intc/Makefile.objs
>> @@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
>> obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
>> obj-$(CONFIG_SH4) += sh_intc.o
>> obj-$(CONFIG_XICS) += xics.o
>> +obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
>> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
>> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
>> obj-$(CONFIG_S390_FLIC) += s390_flic.o
>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> index a715532..6ca391f 100644
>> --- a/hw/intc/xics.c
>> +++ b/hw/intc/xics.c
>> @@ -32,12 +32,11 @@
>> #include "hw/hw.h"
>> #include "trace.h"
>> #include "qemu/timer.h"
>> -#include "hw/ppc/spapr.h"
>> #include "hw/ppc/xics.h"
>> #include "qemu/error-report.h"
>> #include "qapi/visitor.h"
>>
>> -static int get_cpu_index_by_dt_id(int cpu_dt_id)
>> +int get_cpu_index_by_dt_id(int cpu_dt_id)
>
> If this is made public it needs xics_*() name the current one is too
> generic for a global symbol.
Sure. Should we also make icp_set_* as xics_icp_set_* then ?
>
>> {
>> PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
>>
>> @@ -242,7 +241,7 @@ static void icp_resend(XICSState *icp, int server)
>> ics_resend(icp->ics);
>> }
>>
>> -static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
>> +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
>> {
>> ICPState *ss = icp->ss + server;
>> uint8_t old_cppr;
>> @@ -266,7 +265,7 @@ static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
>> }
>> }
>>
>> -static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
>> +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
>> {
>> ICPState *ss = icp->ss + server;
>>
>> @@ -276,7 +275,7 @@ static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
>> }
>> }
>>
>> -static uint32_t icp_accept(ICPState *ss)
>> +uint32_t icp_accept(ICPState *ss)
>> {
>> uint32_t xirr = ss->xirr;
>>
>> @@ -289,7 +288,7 @@ static uint32_t icp_accept(ICPState *ss)
>> return xirr;
>> }
>>
>> -static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
>> +void icp_eoi(XICSState *icp, int server, uint32_t xirr)
>> {
>> ICPState *ss = icp->ss + server;
>>
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file
2016-06-24 5:57 ` Nikunj A Dadhania
@ 2016-06-24 6:12 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-24 6:12 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 4496 bytes --]
On Fri, Jun 24, 2016 at 11:27:58AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Thu, Jun 23, 2016 at 11:17:21PM +0530, Nikunj A Dadhania wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> Leave the core ICP/ICS logic in xics.c and move the top level
> >> class wrapper, hypercall and RTAS handlers to xics_spapr.c
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> [add cpu.h in xics_spapr.c, move set_nr_irqs and set_nr_servers to
> >> xics_spapr.c]
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> default-configs/ppc64-softmmu.mak | 1 +
> >> hw/intc/Makefile.objs | 1 +
> >> hw/intc/xics.c | 418 +-----------------------------------
> >> hw/intc/xics_spapr.c | 432 ++++++++++++++++++++++++++++++++++++++
> >> include/hw/ppc/xics.h | 21 ++
> >> 5 files changed, 464 insertions(+), 409 deletions(-)
> >> create mode 100644 hw/intc/xics_spapr.c
> >>
> >> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
> >> index bb71b23..c4be59f 100644
> >> --- a/default-configs/ppc64-softmmu.mak
> >> +++ b/default-configs/ppc64-softmmu.mak
> >> @@ -49,6 +49,7 @@ CONFIG_ETSEC=y
> >> CONFIG_LIBDECNUMBER=y
> >> # For pSeries
> >> CONFIG_XICS=$(CONFIG_PSERIES)
> >> +CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
> >> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
> >> # For PReP
> >> CONFIG_MC146818RTC=y
> >> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> >> index c7bbf88..530df2e 100644
> >> --- a/hw/intc/Makefile.objs
> >> +++ b/hw/intc/Makefile.objs
> >> @@ -30,6 +30,7 @@ obj-$(CONFIG_OPENPIC_KVM) += openpic_kvm.o
> >> obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
> >> obj-$(CONFIG_SH4) += sh_intc.o
> >> obj-$(CONFIG_XICS) += xics.o
> >> +obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
> >> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
> >> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
> >> obj-$(CONFIG_S390_FLIC) += s390_flic.o
> >> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> >> index a715532..6ca391f 100644
> >> --- a/hw/intc/xics.c
> >> +++ b/hw/intc/xics.c
> >> @@ -32,12 +32,11 @@
> >> #include "hw/hw.h"
> >> #include "trace.h"
> >> #include "qemu/timer.h"
> >> -#include "hw/ppc/spapr.h"
> >> #include "hw/ppc/xics.h"
> >> #include "qemu/error-report.h"
> >> #include "qapi/visitor.h"
> >>
> >> -static int get_cpu_index_by_dt_id(int cpu_dt_id)
> >> +int get_cpu_index_by_dt_id(int cpu_dt_id)
> >
> > If this is made public it needs xics_*() name the current one is too
> > generic for a global symbol.
>
> Sure. Should we also make icp_set_* as xics_icp_set_* then ?
I'm happy enough to treat icp_() as sufficient namespacing on its own.
>
> >
> >> {
> >> PowerPCCPU *cpu = ppc_get_vcpu_by_dt_id(cpu_dt_id);
> >>
> >> @@ -242,7 +241,7 @@ static void icp_resend(XICSState *icp, int server)
> >> ics_resend(icp->ics);
> >> }
> >>
> >> -static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> >> +void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> >> {
> >> ICPState *ss = icp->ss + server;
> >> uint8_t old_cppr;
> >> @@ -266,7 +265,7 @@ static void icp_set_cppr(XICSState *icp, int server, uint8_t cppr)
> >> }
> >> }
> >>
> >> -static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> >> +void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> >> {
> >> ICPState *ss = icp->ss + server;
> >>
> >> @@ -276,7 +275,7 @@ static void icp_set_mfrr(XICSState *icp, int server, uint8_t mfrr)
> >> }
> >> }
> >>
> >> -static uint32_t icp_accept(ICPState *ss)
> >> +uint32_t icp_accept(ICPState *ss)
> >> {
> >> uint32_t xirr = ss->xirr;
> >>
> >> @@ -289,7 +288,7 @@ static uint32_t icp_accept(ICPState *ss)
> >> return xirr;
> >> }
> >>
> >> -static void icp_eoi(XICSState *icp, int server, uint32_t xirr)
> >> +void icp_eoi(XICSState *icp, int server, uint32_t xirr)
> >> {
> >> ICPState *ss = icp->ss + server;
> >>
>
> Regards
> Nikunj
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places Nikunj A Dadhania
@ 2016-06-27 3:43 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-27 3:43 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 987 bytes --]
On Thu, Jun 23, 2016 at 11:17:24PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The "ICP" is a different object than the "XICS". For historical reasons,
> we have a number of places where we name a variable "icp" while it contains
> a XICSState pointer. There *is* an ICPState structure too so this makes
> the code really confusing.
>
> This is a mechanical replacement of all those instances to use the name
> "xics" instead. There should be no functional change.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [spapr_cpu_init has been moved to spapr_cpu_core.c, change there]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list Nikunj A Dadhania
@ 2016-06-27 4:20 ` David Gibson
2016-06-27 4:56 ` Nikunj A Dadhania
2016-06-27 4:59 ` Nikunj A Dadhania
0 siblings, 2 replies; 37+ messages in thread
From: David Gibson @ 2016-06-27 4:20 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 23029 bytes --]
On Thu, Jun 23, 2016 at 11:17:25PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Instead of an array of fixed sized blocks, use a list, as we will need
> to have sources with variable number of interrupts. SPAPR only uses
> a single entry. Native will create more. If performance becomes an
> issue we can add some hashed lookup but for now this will do fine.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> hw/intc/xics.c | 78 +++++++++++++++++++++++++++---------------------
> hw/intc/xics_kvm.c | 29 +++++++++++++-----
> hw/intc/xics_spapr.c | 82 +++++++++++++++++++++++++++++----------------------
> hw/ppc/spapr_events.c | 2 +-
> hw/ppc/spapr_pci.c | 5 ++--
> hw/ppc/spapr_vio.c | 2 +-
> include/hw/ppc/xics.h | 13 ++++----
> 7 files changed, 124 insertions(+), 87 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 38e51fc..ef2a1e4 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -96,13 +96,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
> static void xics_common_reset(DeviceState *d)
> {
> XICSState *xics = XICS_COMMON(d);
> + ICSState *ics;
> int i;
>
> for (i = 0; i < xics->nr_servers; i++) {
> device_reset(DEVICE(&xics->ss[i]));
> }
>
> - device_reset(DEVICE(xics->ics));
> + QLIST_FOREACH(ics, &xics->ics, list) {
> + device_reset(DEVICE(ics));
> + }
> }
>
> static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
> @@ -134,7 +137,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
> }
>
> assert(info->set_nr_irqs);
> - assert(xics->ics);
> info->set_nr_irqs(xics, value, errp);
> }
>
> @@ -212,33 +214,35 @@ static void ics_reject(ICSState *ics, int nr);
> static void ics_resend(ICSState *ics);
> static void ics_eoi(ICSState *ics, int nr);
>
> -static void icp_check_ipi(XICSState *xics, int server)
> +static void icp_check_ipi(ICPState *ss, int server)
Since you're now passing ICPState, you don't need the server
parameter, since its only purpose is to locate the right ICPState in
the XICSState.
> {
> - ICPState *ss = xics->ss + server;
> -
> if (XISR(ss) && (ss->pending_priority <= ss->mfrr)) {
> return;
> }
>
> trace_xics_icp_check_ipi(server, ss->mfrr);
>
> - if (XISR(ss)) {
> - ics_reject(xics->ics, XISR(ss));
> + if (XISR(ss) && ss->xirr_owner) {
> + ics_reject(ss->xirr_owner, XISR(ss));
> }
>
> ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
> ss->pending_priority = ss->mfrr;
> + ss->xirr_owner = NULL;
> qemu_irq_raise(ss->output);
> }
>
> static void icp_resend(XICSState *xics, int server)
> {
> ICPState *ss = xics->ss + server;
> + ICSState *ics;
>
> if (ss->mfrr < CPPR(ss)) {
> - icp_check_ipi(xics, server);
> + icp_check_ipi(ss, server);
> + }
> + QLIST_FOREACH(ics, &xics->ics, list) {
> + ics_resend(ics);
> }
> - ics_resend(xics->ics);
> }
>
> void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
> @@ -256,7 +260,10 @@ void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
> ss->xirr &= ~XISR_MASK; /* Clear XISR */
> ss->pending_priority = 0xff;
> qemu_irq_lower(ss->output);
> - ics_reject(xics->ics, old_xisr);
> + if (ss->xirr_owner) {
> + ics_reject(ss->xirr_owner, old_xisr);
> + ss->xirr_owner = NULL;
> + }
> }
> } else {
> if (!XISR(ss)) {
> @@ -271,7 +278,7 @@ void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr)
>
> ss->mfrr = mfrr;
> if (mfrr < CPPR(ss)) {
> - icp_check_ipi(xics, server);
> + icp_check_ipi(ss, server);
> }
> }
>
> @@ -282,6 +289,7 @@ uint32_t icp_accept(ICPState *ss)
> qemu_irq_lower(ss->output);
> ss->xirr = ss->pending_priority << 24;
> ss->pending_priority = 0xff;
> + ss->xirr_owner = NULL;
>
> trace_xics_icp_accept(xirr, ss->xirr);
>
> @@ -299,30 +307,40 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr)
> void icp_eoi(XICSState *xics, int server, uint32_t xirr)
> {
> ICPState *ss = xics->ss + server;
> + ICSState *ics;
> + uint32_t irq;
>
> /* Send EOI -> ICS */
> ss->xirr = (ss->xirr & ~CPPR_MASK) | (xirr & CPPR_MASK);
> trace_xics_icp_eoi(server, xirr, ss->xirr);
> - ics_eoi(xics->ics, xirr & XISR_MASK);
> + irq = xirr & XISR_MASK;
> + QLIST_FOREACH(ics, &xics->ics, list) {
> + if (ics_valid_irq(ics, irq)) {
> + ics_eoi(ics, irq);
> + }
> + }
> if (!XISR(ss)) {
> icp_resend(xics, server);
> }
> }
>
> -static void icp_irq(XICSState *xics, int server, int nr, uint8_t priority)
> +static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
> {
> + XICSState *xics = ics->xics;
> ICPState *ss = xics->ss + server;
>
> trace_xics_icp_irq(server, nr, priority);
>
> if ((priority >= CPPR(ss))
> || (XISR(ss) && (ss->pending_priority <= priority))) {
> - ics_reject(xics->ics, nr);
> + ics_reject(ics, nr);
> } else {
> - if (XISR(ss)) {
> - ics_reject(xics->ics, XISR(ss));
> + if (XISR(ss) && ss->xirr_owner) {
> + ics_reject(ss->xirr_owner, XISR(ss));
> + ss->xirr_owner = NULL;
> }
> ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
> + ss->xirr_owner = ics;
> ss->pending_priority = priority;
> trace_xics_icp_raise(ss->xirr, ss->pending_priority);
> qemu_irq_raise(ss->output);
> @@ -405,8 +423,7 @@ static void resend_msi(ICSState *ics, int srcno)
> if (irq->status & XICS_STATUS_REJECTED) {
> irq->status &= ~XICS_STATUS_REJECTED;
> if (irq->priority != 0xff) {
> - icp_irq(ics->xics, irq->server, srcno + ics->offset,
> - irq->priority);
> + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
> }
> }
> }
> @@ -419,7 +436,7 @@ static void resend_lsi(ICSState *ics, int srcno)
> && (irq->status & XICS_STATUS_ASSERTED)
> && !(irq->status & XICS_STATUS_SENT)) {
> irq->status |= XICS_STATUS_SENT;
> - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
> + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
> }
> }
>
> @@ -434,7 +451,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
> irq->status |= XICS_STATUS_MASKED_PENDING;
> trace_xics_masked_pending();
> } else {
> - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
> + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
> }
> }
> }
> @@ -473,7 +490,7 @@ static void write_xive_msi(ICSState *ics, int srcno)
> }
>
> irq->status &= ~XICS_STATUS_MASKED_PENDING;
> - icp_irq(ics->xics, irq->server, srcno + ics->offset, irq->priority);
> + icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
> }
>
> static void write_xive_lsi(ICSState *ics, int srcno)
> @@ -659,28 +676,23 @@ static const TypeInfo ics_info = {
> /*
> * Exported functions
> */
> -int xics_find_source(XICSState *xics, int irq)
> +ICSState *xics_find_source(XICSState *xics, int irq)
> {
> - int sources = 1;
> - int src;
> + ICSState *ics;
>
> - /* FIXME: implement multiple sources */
> - for (src = 0; src < sources; ++src) {
> - ICSState *ics = &xics->ics[src];
> + QLIST_FOREACH(ics, &xics->ics, list) {
> if (ics_valid_irq(ics, irq)) {
> - return src;
> + return ics;
> }
> }
> -
> - return -1;
> + return NULL;
> }
>
> qemu_irq xics_get_qirq(XICSState *xics, int irq)
> {
> - int src = xics_find_source(xics, irq);
> + ICSState *ics = xics_find_source(xics, irq);
>
> - if (src >= 0) {
> - ICSState *ics = &xics->ics[src];
> + if (ics) {
> return ics->qirqs[irq - ics->offset];
> }
>
> diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c
> index 64d2256..75b3290 100644
> --- a/hw/intc/xics_kvm.c
> +++ b/hw/intc/xics_kvm.c
> @@ -365,7 +365,13 @@ static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
> static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
> Error **errp)
> {
> - xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
> + ICSState *ics = QLIST_FIRST(&xics->ics);
> +
> + /* This needs to be deprecated ... */
> + xics->nr_irqs = nr_irqs;
> + if (ics) {
> + ics->nr_irqs = nr_irqs;
> + }
> }
>
> static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
> @@ -398,6 +404,7 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
> {
> KVMXICSState *xicskvm = KVM_XICS(dev);
> XICSState *xics = XICS_COMMON(dev);
> + ICSState *ics;
> int i, rc;
> Error *error = NULL;
> struct kvm_create_device xics_create_device = {
> @@ -449,10 +456,12 @@ static void xics_kvm_realize(DeviceState *dev, Error **errp)
>
> xicskvm->kernel_xics_fd = xics_create_device.fd;
>
> - object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
> - if (error) {
> - error_propagate(errp, error);
> - goto fail;
> + QLIST_FOREACH(ics, &xics->ics, list) {
> + object_property_set_bool(OBJECT(ics), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + goto fail;
> + }
> }
>
> assert(xics->nr_servers);
> @@ -481,10 +490,14 @@ fail:
> static void xics_kvm_initfn(Object *obj)
> {
> XICSState *xics = XICS_COMMON(obj);
> + ICSState *ics;
> +
> + QLIST_INIT(&xics->ics);
>
> - xics->ics = ICS(object_new(TYPE_KVM_ICS));
> - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
> - xics->ics->xics = xics;
> + ics = ICS(object_new(TYPE_KVM_ICS));
> + object_property_add_child(obj, "ics", OBJECT(ics), NULL);
> + ics->xics = xics;
> + QLIST_INSERT_HEAD(&xics->ics, ics, list);
> }
>
> static void xics_kvm_class_init(ObjectClass *oc, void *data)
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index eda15a6..b03dd0d 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -113,10 +113,10 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nargs, target_ulong args,
> uint32_t nret, target_ulong rets)
> {
> - ICSState *ics = spapr->xics->ics;
> + ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> uint32_t nr, server, priority;
>
> - if ((nargs != 3) || (nret != 1)) {
> + if ((nargs != 3) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
!ice should surely be an assert, or at least a HW_ERROR, not a PARAM_ERROR.
> }
> @@ -141,10 +141,10 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nargs, target_ulong args,
> uint32_t nret, target_ulong rets)
> {
> - ICSState *ics = spapr->xics->ics;
> + ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> uint32_t nr;
>
> - if ((nargs != 1) || (nret != 3)) {
> + if ((nargs != 1) || (nret != 3) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
> @@ -166,10 +166,10 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nargs, target_ulong args,
> uint32_t nret, target_ulong rets)
> {
> - ICSState *ics = spapr->xics->ics;
> + ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> uint32_t nr;
>
> - if ((nargs != 1) || (nret != 1)) {
> + if ((nargs != 1) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
> @@ -192,10 +192,10 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nargs, target_ulong args,
> uint32_t nret, target_ulong rets)
> {
> - ICSState *ics = spapr->xics->ics;
> + ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> uint32_t nr;
>
> - if ((nargs != 1) || (nret != 1)) {
> + if ((nargs != 1) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
> @@ -217,7 +217,13 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
> Error **errp)
> {
> - xics->nr_irqs = xics->ics->nr_irqs = nr_irqs;
> + ICSState *ics = QLIST_FIRST(&xics->ics);
> +
> + /* This needs to be deprecated ... */
> + xics->nr_irqs = nr_irqs;
> + if (ics) {
> + ics->nr_irqs = nr_irqs;
> + }
> }
>
> static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
> @@ -240,6 +246,7 @@ static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_servers,
> static void xics_spapr_realize(DeviceState *dev, Error **errp)
> {
> XICSState *xics = XICS(dev);
> + ICSState *ics;
> Error *error = NULL;
> int i;
>
> @@ -261,10 +268,12 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
> spapr_register_hypercall(H_EOI, h_eoi);
> spapr_register_hypercall(H_IPOLL, h_ipoll);
>
> - object_property_set_bool(OBJECT(xics->ics), true, "realized", &error);
> - if (error) {
> - error_propagate(errp, error);
> - return;
> + QLIST_FOREACH(ics, &xics->ics, list) {
> + object_property_set_bool(OBJECT(ics), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> }
>
> for (i = 0; i < xics->nr_servers; i++) {
> @@ -280,10 +289,14 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
> static void xics_spapr_initfn(Object *obj)
> {
> XICSState *xics = XICS(obj);
> + ICSState *ics;
> +
> + QLIST_INIT(&xics->ics);
>
> - xics->ics = ICS(object_new(TYPE_ICS));
> - object_property_add_child(obj, "ics", OBJECT(xics->ics), NULL);
> - xics->ics->xics = xics;
> + ics = ICS(object_new(TYPE_ICS));
> + object_property_add_child(obj, "ics", OBJECT(ics), NULL);
> + ics->xics = xics;
> + QLIST_INSERT_HEAD(&xics->ics, ics, list);
> }
>
> static void xics_spapr_class_init(ObjectClass *oc, void *data)
> @@ -329,14 +342,15 @@ static int ics_find_free_block(ICSState *ics, int num, int alignnum)
> return -1;
> }
>
> -int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
> - Error **errp)
> +int xics_spapr_alloc(XICSState *xics, int irq_hint, bool lsi, Error **errp)
> {
> - ICSState *ics = &xics->ics[src];
> + ICSState *ics = QLIST_FIRST(&xics->ics);
> int irq;
>
> + if (!ics) {
> + return -1;
> + }
> if (irq_hint) {
> - assert(src == xics_find_source(xics, irq_hint));
> if (!ICS_IRQ_FREE(ics, irq_hint - ics->offset)) {
> error_setg(errp, "can't allocate IRQ %d: already in use", irq_hint);
> return -1;
> @@ -352,7 +366,7 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
> }
>
> ics_set_irq_type(ics, irq - ics->offset, lsi);
> - trace_xics_alloc(src, irq);
> + trace_xics_alloc(0, irq);
>
> return irq;
> }
> @@ -361,13 +375,16 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
> * Allocate block of consecutive IRQs, and return the number of the first IRQ in
> * the block. If align==true, aligns the first IRQ number to num.
> */
> -int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
> - bool align, Error **errp)
> +int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align,
> + Error **errp)
> {
> + ICSState *ics = QLIST_FIRST(&xics->ics);
> int i, first = -1;
> - ICSState *ics = &xics->ics[src];
Ouch.. AFAICT this would have SEGVed if it was ever called with src != 0.
>
> - assert(src == 0);
> + if (!ics) {
> + return -1;
> + }
> +
> /*
> * MSIMesage::data is used for storing VIRQ so
> * it has to be aligned to num to support multiple
> @@ -394,7 +411,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
> }
> first += ics->offset;
>
> - trace_xics_alloc_block(src, first, num, lsi, align);
> + trace_xics_alloc_block(0, first, num, lsi, align);
You should remove the src from the trave definition since it has to be 0.
>
> return first;
> }
> @@ -405,7 +422,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
>
> for (i = srcno; i < srcno + num; ++i) {
> if (ICS_IRQ_FREE(ics, i)) {
> - trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
> + trace_xics_ics_free_warn(0, i + ics->offset);
Likewise here you should remove the always 0 parameter from the trace definition.
> }
> memset(&ics->irqs[i], 0, sizeof(ICSIRQState));
> }
> @@ -413,15 +430,10 @@ static void ics_free(ICSState *ics, int srcno, int num)
>
> void xics_spapr_free(XICSState *xics, int irq, int num)
> {
> - int src = xics_find_source(xics, irq);
> -
> - if (src >= 0) {
> - ICSState *ics = &xics->ics[src];
> -
> - /* FIXME: implement multiple sources */
> - assert(src == 0);
> + ICSState *ics = xics_find_source(xics, irq);
>
> - trace_xics_ics_free(ics - xics->ics, irq, num);
> + if (ics) {
> + trace_xics_ics_free(0, irq, num);
> ics_free(ics, irq - ics->offset, num);
> }
> }
> diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c
> index b0668b3..adf8da4 100644
> --- a/hw/ppc/spapr_events.c
> +++ b/hw/ppc/spapr_events.c
> @@ -603,7 +603,7 @@ out_no_events:
> void spapr_events_init(sPAPRMachineState *spapr)
> {
> QTAILQ_INIT(&spapr->pending_events);
> - spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, 0, false,
> + spapr->check_exception_irq = xics_spapr_alloc(spapr->xics, 0, false,
> &error_fatal);
> spapr->epow_notifier.notify = spapr_powerdown_req;
> qemu_register_powerdown_notifier(&spapr->epow_notifier);
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 8c1e6b1..3d08c0a 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -360,7 +360,7 @@ static void rtas_ibm_change_msi(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> }
>
> /* Allocate MSIs */
> - irq = xics_spapr_alloc_block(spapr->xics, 0, req_num, false,
> + irq = xics_spapr_alloc_block(spapr->xics, req_num, false,
> ret_intr_type == RTAS_TYPE_MSI, &err);
> if (err) {
> error_reportf_err(err, "Can't allocate MSIs for device %x: ",
> @@ -1442,8 +1442,7 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp)
> uint32_t irq;
> Error *local_err = NULL;
>
> - irq = xics_spapr_alloc_block(spapr->xics, 0, 1, true, false,
> - &local_err);
> + irq = xics_spapr_alloc_block(spapr->xics, 1, true, false, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> error_prepend(errp, "can't allocate LSIs: ");
> diff --git a/hw/ppc/spapr_vio.c b/hw/ppc/spapr_vio.c
> index f93244d..22360af 100644
> --- a/hw/ppc/spapr_vio.c
> +++ b/hw/ppc/spapr_vio.c
> @@ -463,7 +463,7 @@ static void spapr_vio_busdev_realize(DeviceState *qdev, Error **errp)
> dev->qdev.id = id;
> }
>
> - dev->irq = xics_spapr_alloc(spapr->xics, 0, dev->irq, false, &local_err);
> + dev->irq = xics_spapr_alloc(spapr->xics, dev->irq, false, &local_err);
> if (local_err) {
> error_propagate(errp, local_err);
> return;
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index c9f0ad7..be96fd8 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -83,7 +83,7 @@ struct XICSState {
> uint32_t nr_servers;
> uint32_t nr_irqs;
> ICPState *ss;
> - ICSState *ics;
> + QLIST_HEAD(, ICSState) ics;
> };
>
> #define TYPE_ICP "icp"
> @@ -109,6 +109,7 @@ struct ICPState {
> DeviceState parent_obj;
> /*< public >*/
> CPUState *cs;
> + ICSState *xirr_owner;
> uint32_t xirr;
> uint8_t pending_priority;
> uint8_t mfrr;
> @@ -143,6 +144,7 @@ struct ICSState {
> qemu_irq *qirqs;
> ICSIRQState *irqs;
> XICSState *xics;
> + QLIST_ENTRY(ICSState) list;
> };
>
> static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
> @@ -170,10 +172,9 @@ struct ICSIRQState {
> #define XICS_IRQS_SPAPR 1024
>
> qemu_irq xics_get_qirq(XICSState *icp, int irq);
> -int xics_spapr_alloc(XICSState *icp, int src, int irq_hint, bool lsi,
> - Error **errp);
> -int xics_spapr_alloc_block(XICSState *icp, int src, int num, bool lsi,
> - bool align, Error **errp);
> +int xics_spapr_alloc(XICSState *icp, int irq_hint, bool lsi, Error **errp);
> +int xics_spapr_alloc_block(XICSState *icp, int num, bool lsi, bool align,
> + Error **errp);
> void xics_spapr_free(XICSState *icp, int irq, int num);
>
> void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
> @@ -193,6 +194,6 @@ void ics_write_xive(ICSState *ics, int nr, int server,
>
> void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
>
> -int xics_find_source(XICSState *icp, int irq);
> +ICSState *xics_find_source(XICSState *icp, int irq);
>
> #endif /* __XICS_H__ */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS Nikunj A Dadhania
@ 2016-06-27 4:21 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-27 4:21 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 2524 bytes --]
On Thu, Jun 23, 2016 at 11:17:27PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> [Move object allocation and adding child to the helper]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> hw/intc/xics.c | 10 ++++++++++
> hw/intc/xics_spapr.c | 7 +------
> include/hw/ppc/xics.h | 1 +
> 3 files changed, 12 insertions(+), 6 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index ef2a1e4..326d21f 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -108,6 +108,16 @@ static void xics_common_reset(DeviceState *d)
> }
> }
>
> +void xics_add_ics(XICSState *xics)
> +{
> + ICSState *ics;
> +
> + ics = ICS(object_new(TYPE_ICS));
> + object_property_add_child(OBJECT(xics), "ics", OBJECT(ics), NULL);
> + ics->xics = xics;
> + QLIST_INSERT_HEAD(&xics->ics, ics, list);
> +}
> +
> static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
> void *opaque, Error **errp)
> {
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index b03dd0d..8acafd9 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -289,14 +289,9 @@ static void xics_spapr_realize(DeviceState *dev, Error **errp)
> static void xics_spapr_initfn(Object *obj)
> {
> XICSState *xics = XICS(obj);
> - ICSState *ics;
>
> QLIST_INIT(&xics->ics);
> -
> - ics = ICS(object_new(TYPE_ICS));
> - object_property_add_child(obj, "ics", OBJECT(ics), NULL);
> - ics->xics = xics;
> - QLIST_INSERT_HEAD(&xics->ics, ics, list);
> + xics_add_ics(xics);
> }
>
> static void xics_spapr_class_init(ObjectClass *oc, void *data)
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 3c63c36..ee0fce2 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -195,5 +195,6 @@ void ics_write_xive(ICSState *ics, int nr, int server,
> void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
>
> ICSState *xics_find_source(XICSState *icp, int irq);
> +void xics_add_ics(XICSState *xics);
>
> #endif /* __XICS_H__ */
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class Nikunj A Dadhania
@ 2016-06-27 4:26 ` David Gibson
2016-06-27 5:18 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-27 4:26 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 16155 bytes --]
On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> The existing implementation remains same and ics-base is introduced.
>
> This will allow different implementations for the source controllers
> such as the MSI support of PHB3 on Power8 which uses in-memory state
> tables for example.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
> hw/intc/xics_spapr.c | 36 ++++++++++--------
> include/hw/ppc/xics.h | 11 +++++-
> 3 files changed, 97 insertions(+), 51 deletions(-)
>
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index 326d21f..e2aa48d 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
> #define CPPR(ss) (((ss)->xirr) >> 24)
>
> -static void ics_reject(ICSState *ics, int nr);
> -static void ics_resend(ICSState *ics);
> -static void ics_eoi(ICSState *ics, int nr);
> +static void ics_base_reject(ICSState *ics, uint32_t nr)
AFICT these will actually work for any of the derived classes, since
they call the function pointer. So I thin the original name was
better than ics_base_*().
> +{
> + ICSStateClass *k = ICS_GET_CLASS(ics);
> +
> + if (k->reject) {
> + k->reject(ics, nr);
> + }
> +}
> +
> +static void ics_base_resend(ICSState *ics)
> +{
> + ICSStateClass *k = ICS_GET_CLASS(ics);
> +
> + if (k->resend) {
> + k->resend(ics);
> + }
> +}
> +
> +static void ics_base_eoi(ICSState *ics, int nr)
> +{
> + ICSStateClass *k = ICS_GET_CLASS(ics);
> +
> + if (k->eoi) {
> + k->eoi(ics, nr);
> + }
> +}
>
> static void icp_check_ipi(ICPState *ss, int server)
> {
> @@ -233,7 +256,7 @@ static void icp_check_ipi(ICPState *ss, int server)
> trace_xics_icp_check_ipi(server, ss->mfrr);
>
> if (XISR(ss) && ss->xirr_owner) {
> - ics_reject(ss->xirr_owner, XISR(ss));
> + ics_base_reject(ss->xirr_owner, XISR(ss));
> }
>
> ss->xirr = (ss->xirr & ~XISR_MASK) | XICS_IPI;
> @@ -251,7 +274,7 @@ static void icp_resend(XICSState *xics, int server)
> icp_check_ipi(ss, server);
> }
> QLIST_FOREACH(ics, &xics->ics, list) {
> - ics_resend(ics);
> + ics_base_resend(ics);
> }
> }
>
> @@ -271,7 +294,7 @@ void icp_set_cppr(XICSState *xics, int server, uint8_t cppr)
> ss->pending_priority = 0xff;
> qemu_irq_lower(ss->output);
> if (ss->xirr_owner) {
> - ics_reject(ss->xirr_owner, old_xisr);
> + ics_base_reject(ss->xirr_owner, old_xisr);
> ss->xirr_owner = NULL;
> }
> }
> @@ -325,8 +348,8 @@ void icp_eoi(XICSState *xics, int server, uint32_t xirr)
> trace_xics_icp_eoi(server, xirr, ss->xirr);
> irq = xirr & XISR_MASK;
> QLIST_FOREACH(ics, &xics->ics, list) {
> - if (ics_valid_irq(ics, irq)) {
> - ics_eoi(ics, irq);
> + if (ics_base_valid_irq(ics, irq)) {
> + ics_base_eoi(ics, irq);
> }
> }
> if (!XISR(ss)) {
> @@ -343,10 +366,10 @@ static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority)
>
> if ((priority >= CPPR(ss))
> || (XISR(ss) && (ss->pending_priority <= priority))) {
> - ics_reject(ics, nr);
> + ics_base_reject(ics, nr);
> } else {
> if (XISR(ss) && ss->xirr_owner) {
> - ics_reject(ss->xirr_owner, XISR(ss));
> + ics_base_reject(ss->xirr_owner, XISR(ss));
> ss->xirr_owner = NULL;
> }
> ss->xirr = (ss->xirr & ~XISR_MASK) | (nr & XISR_MASK);
> @@ -425,7 +448,7 @@ static const TypeInfo icp_info = {
> /*
> * ICS: Source layer
> */
> -static void resend_msi(ICSState *ics, int srcno)
> +static void ics_resend_msi(ICSState *ics, int srcno)
> {
> ICSIRQState *irq = ics->irqs + srcno;
>
> @@ -438,7 +461,7 @@ static void resend_msi(ICSState *ics, int srcno)
> }
> }
>
> -static void resend_lsi(ICSState *ics, int srcno)
> +static void ics_resend_lsi(ICSState *ics, int srcno)
> {
> ICSIRQState *irq = ics->irqs + srcno;
>
> @@ -450,7 +473,7 @@ static void resend_lsi(ICSState *ics, int srcno)
> }
> }
>
> -static void set_irq_msi(ICSState *ics, int srcno, int val)
> +static void ics_set_irq_msi(ICSState *ics, int srcno, int val)
> {
> ICSIRQState *irq = ics->irqs + srcno;
>
> @@ -466,7 +489,7 @@ static void set_irq_msi(ICSState *ics, int srcno, int val)
> }
> }
>
> -static void set_irq_lsi(ICSState *ics, int srcno, int val)
> +static void ics_set_irq_lsi(ICSState *ics, int srcno, int val)
> {
> ICSIRQState *irq = ics->irqs + srcno;
>
> @@ -476,7 +499,7 @@ static void set_irq_lsi(ICSState *ics, int srcno, int val)
> } else {
> irq->status &= ~XICS_STATUS_ASSERTED;
> }
> - resend_lsi(ics, srcno);
> + ics_resend_lsi(ics, srcno);
> }
>
> static void ics_set_irq(void *opaque, int srcno, int val)
> @@ -484,13 +507,13 @@ static void ics_set_irq(void *opaque, int srcno, int val)
> ICSState *ics = (ICSState *)opaque;
>
> if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
> - set_irq_lsi(ics, srcno, val);
> + ics_set_irq_lsi(ics, srcno, val);
> } else {
> - set_irq_msi(ics, srcno, val);
> + ics_set_irq_msi(ics, srcno, val);
> }
> }
>
> -static void write_xive_msi(ICSState *ics, int srcno)
> +static void ics_write_xive_msi(ICSState *ics, int srcno)
> {
> ICSIRQState *irq = ics->irqs + srcno;
>
> @@ -503,31 +526,30 @@ static void write_xive_msi(ICSState *ics, int srcno)
> icp_irq(ics, irq->server, srcno + ics->offset, irq->priority);
> }
>
> -static void write_xive_lsi(ICSState *ics, int srcno)
> +static void ics_write_xive_lsi(ICSState *ics, int srcno)
> {
> - resend_lsi(ics, srcno);
> + ics_resend_lsi(ics, srcno);
> }
>
> -void ics_write_xive(ICSState *ics, int nr, int server,
> - uint8_t priority, uint8_t saved_priority)
> +void ics_write_xive(ICSState *ics, int srcno, int server,
> + uint8_t priority, uint8_t saved_priority)
> {
> - int srcno = nr - ics->offset;
> ICSIRQState *irq = ics->irqs + srcno;
>
> irq->server = server;
> irq->priority = priority;
> irq->saved_priority = saved_priority;
>
> - trace_xics_ics_write_xive(nr, srcno, server, priority);
> + trace_xics_ics_write_xive(ics->offset + srcno, srcno, server, priority);
>
> if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_LSI) {
> - write_xive_lsi(ics, srcno);
> + ics_write_xive_lsi(ics, srcno);
> } else {
> - write_xive_msi(ics, srcno);
> + ics_write_xive_msi(ics, srcno);
> }
> }
>
> -static void ics_reject(ICSState *ics, int nr)
> +static void ics_reject(ICSState *ics, uint32_t nr)
> {
> ICSIRQState *irq = ics->irqs + nr - ics->offset;
>
> @@ -543,14 +565,14 @@ static void ics_resend(ICSState *ics)
> for (i = 0; i < ics->nr_irqs; i++) {
> /* FIXME: filter by server#? */
> if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
> - resend_lsi(ics, i);
> + ics_resend_lsi(ics, i);
> } else {
> - resend_msi(ics, i);
> + ics_resend_msi(ics, i);
> }
> }
> }
>
> -static void ics_eoi(ICSState *ics, int nr)
> +static void ics_eoi(ICSState *ics, uint32_t nr)
> {
> int srcno = nr - ics->offset;
> ICSIRQState *irq = ics->irqs + srcno;
> @@ -639,7 +661,8 @@ static const VMStateDescription vmstate_ics = {
> VMSTATE_UINT32_EQUAL(nr_irqs, ICSState),
>
> VMSTATE_STRUCT_VARRAY_POINTER_UINT32(irqs, ICSState, nr_irqs,
> - vmstate_ics_irq, ICSIRQState),
> + vmstate_ics_irq,
> + ICSIRQState),
> VMSTATE_END_OF_LIST()
> },
> };
> @@ -672,17 +695,28 @@ static void ics_class_init(ObjectClass *klass, void *data)
> dc->vmsd = &vmstate_ics;
> dc->reset = ics_reset;
> isc->post_load = ics_post_load;
> + isc->reject = ics_reject;
> + isc->resend = ics_resend;
> + isc->eoi = ics_eoi;
> }
>
> static const TypeInfo ics_info = {
> .name = TYPE_ICS,
> - .parent = TYPE_DEVICE,
> + .parent = TYPE_ICS_BASE,
> .instance_size = sizeof(ICSState),
> .class_init = ics_class_init,
> .class_size = sizeof(ICSStateClass),
> .instance_init = ics_initfn,
> };
>
> +static const TypeInfo ics_base_info = {
> + .name = TYPE_ICS_BASE,
> + .parent = TYPE_DEVICE,
> + .abstract = true,
> + .instance_size = sizeof(ICSState),
> + .class_size = sizeof(ICSStateClass),
> +};
> +
> /*
> * Exported functions
> */
> @@ -691,7 +725,7 @@ ICSState *xics_find_source(XICSState *xics, int irq)
> ICSState *ics;
>
> QLIST_FOREACH(ics, &xics->ics, list) {
> - if (ics_valid_irq(ics, irq)) {
> + if (ics_base_valid_irq(ics, irq)) {
> return ics;
> }
> }
> @@ -721,6 +755,7 @@ static void xics_register_types(void)
> {
> type_register_static(&xics_common_info);
> type_register_static(&ics_info);
> + type_register_static(&ics_base_info);
> type_register_static(&icp_info);
> }
>
> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
> index 8acafd9..113b067 100644
> --- a/hw/intc/xics_spapr.c
> +++ b/hw/intc/xics_spapr.c
> @@ -114,7 +114,7 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nret, target_ulong rets)
> {
> ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> - uint32_t nr, server, priority;
> + uint32_t nr, srcno, server, priority;
>
> if ((nargs != 3) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> @@ -125,13 +125,14 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> server = get_cpu_index_by_dt_id(rtas_ld(args, 1));
> priority = rtas_ld(args, 2);
>
> - if (!ics_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
> + if (!ics_base_valid_irq(ics, nr) || (server >= ics->xics->nr_servers)
> || (priority > 0xff)) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
>
> - ics_write_xive(ics, nr, server, priority, priority);
> + srcno = nr - ics->offset;
> + ics_write_xive(ics, srcno, server, priority, priority);
>
> rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> }
> @@ -142,7 +143,7 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nret, target_ulong rets)
> {
> ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> - uint32_t nr;
> + uint32_t nr, srcno;
>
> if ((nargs != 1) || (nret != 3) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> @@ -151,14 +152,15 @@ static void rtas_get_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>
> nr = rtas_ld(args, 0);
>
> - if (!ics_valid_irq(ics, nr)) {
> + if (!ics_base_valid_irq(ics, nr)) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
>
> rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> - rtas_st(rets, 1, ics->irqs[nr - ics->offset].server);
> - rtas_st(rets, 2, ics->irqs[nr - ics->offset].priority);
> + srcno = nr - ics->offset;
> + rtas_st(rets, 1, ics->irqs[srcno].server);
> + rtas_st(rets, 2, ics->irqs[srcno].priority);
> }
>
> static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> @@ -167,7 +169,7 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nret, target_ulong rets)
> {
> ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> - uint32_t nr;
> + uint32_t nr, srcno;
>
> if ((nargs != 1) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> @@ -176,13 +178,14 @@ static void rtas_int_off(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>
> nr = rtas_ld(args, 0);
>
> - if (!ics_valid_irq(ics, nr)) {
> + if (!ics_base_valid_irq(ics, nr)) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
>
> - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server, 0xff,
> - ics->irqs[nr - ics->offset].priority);
> + srcno = nr - ics->offset;
> + ics_write_xive(ics, srcno, ics->irqs[srcno].server, 0xff,
> + ics->irqs[srcno].priority);
>
> rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> }
> @@ -193,7 +196,7 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
> uint32_t nret, target_ulong rets)
> {
> ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
> - uint32_t nr;
> + uint32_t nr, srcno;
>
> if ((nargs != 1) || (nret != 1) || !ics) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> @@ -202,14 +205,15 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>
> nr = rtas_ld(args, 0);
>
> - if (!ics_valid_irq(ics, nr)) {
> + if (!ics_base_valid_irq(ics, nr)) {
> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
> return;
> }
>
> - ics_write_xive(ics, nr, ics->irqs[nr - ics->offset].server,
> - ics->irqs[nr - ics->offset].saved_priority,
> - ics->irqs[nr - ics->offset].saved_priority);
> + srcno = nr - ics->offset;
> + ics_write_xive(ics, srcno, ics->irqs[srcno].server,
> + ics->irqs[srcno].saved_priority,
> + ics->irqs[srcno].saved_priority);
>
> rtas_st(rets, 0, RTAS_OUT_SUCCESS);
> }
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index ee0fce2..6fb1cb4 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -117,6 +117,10 @@ struct ICPState {
> bool cap_irq_xics_enabled;
> };
>
> +#define TYPE_ICS_BASE "ics-base"
> +#define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
> +
> +/* Retain ics for sPAPR for migration from existing sPAPR guests */
> #define TYPE_ICS "ics"
> #define ICS(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS)
>
> @@ -133,6 +137,9 @@ struct ICSStateClass {
>
> void (*pre_save)(ICSState *s);
> int (*post_load)(ICSState *s, int version_id);
> + void (*reject)(ICSState *s, uint32_t irq);
> + void (*resend)(ICSState *s);
> + void (*eoi)(ICSState *s, uint32_t irq);
> };
>
> struct ICSState {
> @@ -147,7 +154,7 @@ struct ICSState {
> QLIST_ENTRY(ICSState) list;
> };
>
> -static inline bool ics_valid_irq(ICSState *ics, uint32_t nr)
> +static inline bool ics_base_valid_irq(ICSState *ics, uint32_t nr)
> {
> return (ics->offset != 0) && (nr >= ics->offset)
> && (nr < (ics->offset + ics->nr_irqs));
> @@ -190,7 +197,7 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr);
> void icp_eoi(XICSState *icp, int server, uint32_t xirr);
>
> void ics_write_xive(ICSState *ics, int nr, int server,
> - uint8_t priority, uint8_t saved_priority);
> + uint8_t priority, uint8_t saved_priority);
>
> void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass Nikunj A Dadhania
@ 2016-06-27 4:36 ` David Gibson
2016-06-27 9:53 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-27 4:36 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 14321 bytes --]
On Thu, Jun 23, 2016 at 11:17:29PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> This provides MMIO based ICP access as found on POWER8
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> default-configs/ppc64-softmmu.mak | 3 +-
> hw/intc/Makefile.objs | 1 +
> hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++++++++
> include/hw/ppc/xics.h | 14 ++
> 4 files changed, 312 insertions(+), 1 deletion(-)
> create mode 100644 hw/intc/xics_native.c
>
> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
> index c4be59f..315e30b 100644
> --- a/default-configs/ppc64-softmmu.mak
> +++ b/default-configs/ppc64-softmmu.mak
> @@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=y
> CONFIG_ETSEC=y
> CONFIG_LIBDECNUMBER=y
> # For pSeries
> -CONFIG_XICS=$(CONFIG_PSERIES)
> +CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV))
> CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
> +CONFIG_XICS_NATIVE=$(CONFIG_POWERNV)
> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
I don't think you've introduced CONFIG_POWERNV in your patches so far,
making this a bit weird.
> # For PReP
> CONFIG_MC146818RTC=y
> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> index 530df2e..f8bbeda 100644
> --- a/hw/intc/Makefile.objs
> +++ b/hw/intc/Makefile.objs
> @@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
> obj-$(CONFIG_SH4) += sh_intc.o
> obj-$(CONFIG_XICS) += xics.o
> obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
> +obj-$(CONFIG_XICS_NATIVE) += xics_native.o
> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
> obj-$(CONFIG_S390_FLIC) += s390_flic.o
> diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c
> new file mode 100644
> index 0000000..26e45cc
> --- /dev/null
> +++ b/hw/intc/xics_native.c
> @@ -0,0 +1,295 @@
> +/*
> + * QEMU PowerPC hardware System Emulator
> + *
> + * Native version of ICS/ICP
> + *
> + * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
Surely this should have yours or Ben's copyright in addition to mine.
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "hw/hw.h"
> +#include "trace.h"
> +#include "qemu/timer.h"
> +#include "hw/ppc/xics.h"
> +#include "qapi/visitor.h"
> +#include "qapi/error.h"
> +
> +#include <libfdt.h>
> +
> +/* #define DEBUG_MM(fmt...) printf(fmt) */
> +#define DEBUG_MM(fmt...) do { } while (0)
> +
> +static void xics_native_initfn(Object *obj)
> +{
> + XICSState *xics = XICS_NATIVE(obj);
> +
> + QLIST_INIT(&xics->ics);
> +}
> +
> +static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width)
> +{
> + XICSState *s = opaque;
> + int32_t cpu_id, server;
> + uint32_t val;
> + ICPState *ss;
> + bool byte0 = (width == 1 && (addr & 0x3) == 0);
> +
> + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
> + server = get_cpu_index_by_dt_id(cpu_id);
Shouldn't each ICP instance register its own MMIO window?
> + if (server < 0) {
> + fprintf(stderr, "XICS: Bad ICP server %d\n", server);
> + goto bad_access;
> + }
> + ss = &s->ss[server];
> + switch (addr & 0xffc) {
> + case 0: /* poll */
> + val = icp_ipoll(ss, NULL);
> + if (byte0) {
> + val >>= 24;
> + } else if (width != 4) {
> + goto bad_access;
> + }
> + break;
> + case 4: /* xirr */
> + if (byte0) {
> + val = icp_ipoll(ss, NULL) >> 24;
> + } else if (width == 4) {
> + val = icp_accept(ss);
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 12:
> + if (byte0) {
> + val = ss->mfrr;
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 16:
> + if (width == 4) {
> + val = ss->links[0];
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 20:
> + if (width == 4) {
> + val = ss->links[1];
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 24:
> + if (width == 4) {
> + val = ss->links[2];
> + } else {
> + goto bad_access;
> + }
> + break;
> + default:
> +bad_access:
> + fprintf(stderr, "XICS: Bad ICP access %llx/%d\n",
> + (unsigned long long)addr, width);
> + val = 0xffffffff;
> + }
> + DEBUG_MM("icp_mm_read(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
> + (unsigned long long)addr, cpu_id, server, (int)(addr & 0xffc),
> + width, val);
> +
> + return val;
> +}
> +
> +static void icp_mm_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned width)
> +{
> + XICSState *s = opaque;
> + int32_t cpu_id, server;
> + ICPState *ss;
> + bool byte0 = (width == 1 && (addr & 0x3) == 0);
> +
> + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
> + server = get_cpu_index_by_dt_id(cpu_id);
> + if (server < 0) {
> + fprintf(stderr, "XICS: Bad ICP server %d\n", server);
> + goto bad_access;
> + }
> + ss = &s->ss[server];
> +
> + DEBUG_MM("icp_mm_write(addr=%016llx,serv=0x%x/%d,off=%d,w=%d,val=0x%08x)\n",
> + (unsigned long long)addr, cpu_id, server,
> + (int)(addr & 0xffc), width, (uint32_t)val);
> +
> + switch (addr & 0xffc) {
> + case 4: /* xirr */
> + if (byte0) {
> + icp_set_cppr(s, server, val);
> + } else if (width == 4) {
> + icp_eoi(s, server, val);
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 12:
> + if (byte0) {
> + icp_set_mfrr(s, server, val);
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 16:
> + if (width == 4) {
> + ss->links[0] = val;
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 20:
> + if (width == 4) {
> + ss->links[1] = val;
> + } else {
> + goto bad_access;
> + }
> + break;
> + case 24:
> + if (width == 4) {
> + ss->links[2] = val;
> + } else {
> + goto bad_access;
> + }
> + break;
> + default:
> + bad_access:
> + val = 0xffffffff;
> + }
> +}
> +
> +static const MemoryRegionOps icp_mm_ops = {
> + .read = icp_mm_read,
> + .write = icp_mm_write,
> + .valid.min_access_size = 1,
> + .valid.max_access_size = 4,
> + .impl.min_access_size = 1,
> + .impl.max_access_size = 4,
> + .endianness = DEVICE_BIG_ENDIAN,
> +};
> +
> +#define _FDT(exp) \
> + do { \
> + int ret = (exp); \
> + if (ret < 0) { \
> + fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
> + #exp, fdt_strerror(ret)); \
> + exit(1); \
> + } \
> + } while (0)
Ugh, I have got to find time to push by qdt cleanup stuff again. Not
within scope for this patch obviously, though.
> +void xics_create_native_icp_node(XICSState *s, void *fdt,
> + uint32_t base, uint32_t count)
> +{
> + uint64_t addr;
> + char *name;
> + const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp";
> + uint32_t irange[2], i, rsize;
> + uint64_t *reg;
> +
> + addr = ICP_MM_BASE | (base << 12);
> +
> + irange[0] = cpu_to_be32(base);
> + irange[1] = cpu_to_be32(count);
> +
> + rsize = sizeof(uint64_t) * 2 * count;
> + reg = g_malloc(rsize);
> + for (i = 0; i < count; i++) {
> + reg[i * 2] = cpu_to_be64(addr | ((base + i) * 0x1000));
> + reg[i * 2 + 1] = cpu_to_be64(0x1000);
> + }
> +
> + name = g_strdup_printf("interrupt-controller@%"PRIX64, addr);
> +
> + /* interrupt controller */
> + _FDT((fdt_begin_node(fdt, name)));
> + g_free(name);
> +
> + _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat))));
> + _FDT((fdt_property(fdt, "reg", reg, rsize)));
> + _FDT((fdt_property_string(fdt, "device_type",
> + "PowerPC-External-Interrupt-Presentation")));
> + _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0)));
> + _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges",
> + irange, sizeof(irange))));
> + _FDT((fdt_property_cell(fdt, "#interrupt-cells", 1)));
> + _FDT((fdt_property_cell(fdt, "#address-cells", 0)));
> + _FDT((fdt_end_node(fdt)));
> +}
> +
> +static void xics_native_realize(DeviceState *dev, Error **errp)
> +{
> + XICSState *s = XICS_NATIVE(dev);
> + SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
> + Error *error = NULL;
> + int i;
> +
> + if (!s->nr_servers) {
> + error_setg(errp, "Number of servers needs to be greater 0");
> + return;
> + }
> +
> + /* Register MMIO regions */
> + memory_region_init_io(&s->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp",
> + ICP_MM_SIZE);
> + sysbus_init_mmio(sbd, &s->icp_mmio);
> + sysbus_mmio_map(sbd, 0, ICP_MM_BASE);
> +
> + for (i = 0; i < s->nr_servers; i++) {
> + object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &error);
> + if (error) {
> + error_propagate(errp, error);
> + return;
> + }
> + }
> +}
> +
> +static void xics_native_class_init(ObjectClass *oc, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(oc);
> + XICSStateClass *xsc = XICS_NATIVE_CLASS(oc);
> +
> + dc->realize = xics_native_realize;
> + xsc->set_nr_servers = xics_set_nr_servers;
> +}
> +
> +static const TypeInfo xics_native_info = {
> + .name = TYPE_XICS_NATIVE,
> + .parent = TYPE_XICS_COMMON,
> + .instance_size = sizeof(XICSState),
> + .class_size = sizeof(XICSStateClass),
> + .class_init = xics_native_class_init,
> + .instance_init = xics_native_initfn,
> +};
> +
> +static void xics_native_register_types(void)
> +{
> + type_register_static(&xics_native_info);
> +}
> +type_init(xics_native_register_types)
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 6fb1cb4..0e47ecb 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -42,6 +42,9 @@
> #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
> #define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM)
>
> +#define TYPE_XICS_NATIVE "xics-native"
> +#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE)
> +
> #define XICS_COMMON_CLASS(klass) \
> OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON)
> #define XICS_SPAPR_CLASS(klass) \
> @@ -50,6 +53,8 @@
> OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON)
> #define XICS_SPAPR_GET_CLASS(obj) \
> OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR)
> +#define XICS_NATIVE_CLASS(klass) \
> + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_NATIVE)
>
> #define XICS_IPI 0x2
> #define XICS_BUID 0x1
> @@ -84,6 +89,7 @@ struct XICSState {
> uint32_t nr_irqs;
> ICPState *ss;
> QLIST_HEAD(, ICSState) ics;
> + MemoryRegion icp_mmio;
This is only used by XICSNative, so it should be in a structure just
for the subclass, not in the common struct.
> };
>
> #define TYPE_ICP "icp"
> @@ -115,8 +121,13 @@ struct ICPState {
> uint8_t mfrr;
> qemu_irq output;
> bool cap_irq_xics_enabled;
> + uint32_t links[3];
Likewise here.
> };
>
> +/* This should be an XSCOM BAR ... the size is arbitrary as well */
> +#define ICP_MM_BASE 0x0003FFFF80000000
> +#define ICP_MM_SIZE 0x0000000010000000
> +
> #define TYPE_ICS_BASE "ics-base"
> #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE)
>
> @@ -187,6 +198,9 @@ void xics_spapr_free(XICSState *icp, int irq, int num);
> void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
> void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu);
>
> +void xics_create_native_icp_node(XICSState *s, void *fdt,
> + uint32_t base, uint32_t count);
> +
> /* Internal XICS interfaces */
> int get_cpu_index_by_dt_id(int cpu_dt_id);
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command Nikunj A Dadhania
@ 2016-06-27 4:48 ` David Gibson
2016-06-27 5:56 ` Benjamin Herrenschmidt
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-27 4:48 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 5818 bytes --]
On Thu, Jun 23, 2016 at 11:17:30PM +0530, Nikunj A Dadhania wrote:
> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>
> Useful to debug interrupt problems.
I'm a bit dubious about this, since I'm not sure info pic really has
much purpose at all. I posted a patch a while back to remove it
entirely, but it didn't go far for lack of interested, and so far I
didn't get time to revisit it and try pushing.
>
> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> hmp-commands-info.hx | 2 ++
> hw/intc/xics.c | 38 ++++++++++++++++++++++++++++++++++++++
> hw/ppc/ppc.c | 14 ++++++++++++++
> include/hw/ppc/ppc.h | 1 +
> include/hw/ppc/xics.h | 2 ++
> monitor.c | 4 ++++
> 6 files changed, 61 insertions(+)
>
> diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
> index 7da9e6c..e4b90b9 100644
> --- a/hmp-commands-info.hx
> +++ b/hmp-commands-info.hx
> @@ -203,6 +203,8 @@ ETEXI
> .mhandler.cmd = sun4m_hmp_info_pic,
> #elif defined(TARGET_LM32)
> .mhandler.cmd = lm32_hmp_info_pic,
> +#elif defined(TARGET_PPC)
> + .mhandler.cmd = ppc_hmp_info_pic,
> #else
> .mhandler.cmd = hmp_info_pic,
> #endif
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index e2aa48d..19eeea9 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -35,6 +35,9 @@
> #include "hw/ppc/xics.h"
> #include "qemu/error-report.h"
> #include "qapi/visitor.h"
> +#include "monitor/monitor.h"
> +
> +static XICSState *g_xics;
>
> int get_cpu_index_by_dt_id(int cpu_dt_id)
> {
> @@ -192,6 +195,9 @@ static void xics_common_initfn(Object *obj)
> object_property_add(obj, "nr_servers", "int",
> xics_prop_get_nr_servers, xics_prop_set_nr_servers,
> NULL, NULL, NULL);
> +
> + /* For exclusive use of monitor command */
> + g_xics = XICS_COMMON(obj);
> }
>
> static void xics_common_class_init(ObjectClass *oc, void *data)
> @@ -636,6 +642,38 @@ static int ics_dispatch_post_load(void *opaque, int version_id)
> return 0;
> }
>
> +void xics_hmp_info_pic(Monitor *mon, const QDict *qdict)
> +{
> + ICSState *ics;
> + uint32_t i;
> +
> + for (i = 0; i < g_xics->nr_servers; i++) {
> + ICPState *icp = &g_xics->ss[i];
> +
> + if (!icp->output) {
> + continue;
> + }
> + monitor_printf(mon, "CPU %d XIRR=%08x (%p) PP=%02x MFRR=%02x\n",
> + i, icp->xirr, icp->xirr_owner,
> + icp->pending_priority, icp->mfrr);
> + }
> + QLIST_FOREACH(ics, &g_xics->ics, list) {
> + monitor_printf(mon, "ICS %4x..%4x %p\n",
> + ics->offset, ics->offset + ics->nr_irqs - 1, ics);
> + for (i = 0; i < ics->nr_irqs; i++) {
> + ICSIRQState *irq = ics->irqs + i;
> +
> + if (!(irq->flags & XICS_FLAGS_IRQ_MASK)) {
> + continue;
> + }
> + monitor_printf(mon, " %4x %s %02x %02x\n",
> + ics->offset + i,
> + (irq->flags & XICS_FLAGS_IRQ_LSI) ? "LSI" : "MSI",
> + irq->priority, irq->status);
> + }
> + }
> +}
> +
> static const VMStateDescription vmstate_ics_irq = {
> .name = "ics/irq",
> .version_id = 2,
> diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c
> index 1bcf740..f3ee1d6 100644
> --- a/hw/ppc/ppc.c
> +++ b/hw/ppc/ppc.c
> @@ -27,6 +27,7 @@
> #include "hw/hw.h"
> #include "hw/ppc/ppc.h"
> #include "hw/ppc/ppc_e500.h"
> +#include "hw/i386/pc.h"
> #include "qemu/timer.h"
> #include "sysemu/sysemu.h"
> #include "sysemu/cpus.h"
> @@ -38,6 +39,10 @@
> #include "kvm_ppc.h"
> #include "trace.h"
>
> +#if defined(TARGET_PPC64)
> +#include "hw/ppc/xics.h"
> +#endif
> +
> //#define PPC_DEBUG_IRQ
> //#define PPC_DEBUG_TB
>
> @@ -1343,3 +1348,12 @@ PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id)
>
> return NULL;
> }
> +
> +void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict)
> +{
> + /* Call in turn every PIC around. OpenPIC doesn't have one yet */
> +#ifdef TARGET_PPC64
> + xics_hmp_info_pic(mon, qdict);
> +#endif
This will break if you have a ppc64 build which doesn't include
XICS.
> + hmp_info_pic(mon, qdict);
> +}
> diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h
> index 5617dc4..8076797 100644
> --- a/include/hw/ppc/ppc.h
> +++ b/include/hw/ppc/ppc.h
> @@ -3,6 +3,7 @@
>
> #include "target-ppc/cpu-qom.h"
>
> +void ppc_hmp_info_pic(Monitor *mon, const QDict *qdict);
> void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level);
>
> /* PowerPC hardware exceptions management helpers */
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 0e47ecb..1dbfa2c 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -218,4 +218,6 @@ void ics_set_irq_type(ICSState *ics, int srcno, bool lsi);
> ICSState *xics_find_source(XICSState *icp, int irq);
> void xics_add_ics(XICSState *xics);
>
> +void xics_hmp_info_pic(Monitor *mon, const QDict *qdict);
> +
> #endif /* __XICS_H__ */
> diff --git a/monitor.c b/monitor.c
> index 6f960f1..66d682b 100644
> --- a/monitor.c
> +++ b/monitor.c
> @@ -94,6 +94,10 @@
> #include "hw/s390x/storage-keys.h"
> #endif
>
> +#if defined(TARGET_PPC)
> +#include "hw/ppc/ppc.h"
> +#endif
> +
> /*
> * Supported types:
> *
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-27 4:20 ` David Gibson
@ 2016-06-27 4:56 ` Nikunj A Dadhania
2016-06-27 5:30 ` David Gibson
2016-06-27 4:59 ` Nikunj A Dadhania
1 sibling, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 4:56 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Thu, Jun 23, 2016 at 11:17:25PM +0530, Nikunj A Dadhania wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> Instead of an array of fixed sized blocks, use a list, as we will need
>> to have sources with variable number of interrupts. SPAPR only uses
>> a single entry. Native will create more. If performance becomes an
>> issue we can add some hashed lookup but for now this will do fine.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> hw/intc/xics.c | 78 +++++++++++++++++++++++++++---------------------
>> hw/intc/xics_kvm.c | 29 +++++++++++++-----
>> hw/intc/xics_spapr.c | 82 +++++++++++++++++++++++++++++----------------------
>> hw/ppc/spapr_events.c | 2 +-
>> hw/ppc/spapr_pci.c | 5 ++--
>> hw/ppc/spapr_vio.c | 2 +-
>> include/hw/ppc/xics.h | 13 ++++----
>> 7 files changed, 124 insertions(+), 87 deletions(-)
>>
>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> index 38e51fc..ef2a1e4 100644
>> --- a/hw/intc/xics.c
>> +++ b/hw/intc/xics.c
>> @@ -96,13 +96,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
>> static void xics_common_reset(DeviceState *d)
>> {
>> XICSState *xics = XICS_COMMON(d);
>> + ICSState *ics;
>> int i;
>>
>> for (i = 0; i < xics->nr_servers; i++) {
>> device_reset(DEVICE(&xics->ss[i]));
>> }
>>
>> - device_reset(DEVICE(xics->ics));
>> + QLIST_FOREACH(ics, &xics->ics, list) {
>> + device_reset(DEVICE(ics));
>> + }
>> }
>>
>> static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
>> @@ -134,7 +137,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
>> }
>>
>> assert(info->set_nr_irqs);
>> - assert(xics->ics);
>> info->set_nr_irqs(xics, value, errp);
>> }
>>
>> @@ -212,33 +214,35 @@ static void ics_reject(ICSState *ics, int nr);
>> static void ics_resend(ICSState *ics);
>> static void ics_eoi(ICSState *ics, int nr);
>>
>> -static void icp_check_ipi(XICSState *xics, int server)
>> +static void icp_check_ipi(ICPState *ss, int server)
>
> Since you're now passing ICPState, you don't need the server
> parameter, since its only purpose is to locate the right ICPState in
> the XICSState.
Right, i had retained this as there was a trace function using it. Maybe
we can then move the trace to the caller.
>> @@ -361,13 +375,16 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
>> * Allocate block of consecutive IRQs, and return the number of the first IRQ in
>> * the block. If align==true, aligns the first IRQ number to num.
>> */
>> -int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
>> - bool align, Error **errp)
>> +int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align,
>> + Error **errp)
>> {
>> + ICSState *ics = QLIST_FIRST(&xics->ics);
>> int i, first = -1;
>> - ICSState *ics = &xics->ics[src];
>
> Ouch.. AFAICT this would have SEGVed if it was ever called with src != 0.
>
>>
>> - assert(src == 0);
>> + if (!ics) {
>> + return -1;
>> + }
>> +
>> /*
>> * MSIMesage::data is used for storing VIRQ so
>> * it has to be aligned to num to support multiple
>> @@ -394,7 +411,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
>> }
>> first += ics->offset;
>>
>> - trace_xics_alloc_block(src, first, num, lsi, align);
>> + trace_xics_alloc_block(0, first, num, lsi, align);
>
> You should remove the src from the trave definition since it has to be
> 0.
Sure.
>>
>> return first;
>> }
>> @@ -405,7 +422,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
>>
>> for (i = srcno; i < srcno + num; ++i) {
>> if (ICS_IRQ_FREE(ics, i)) {
>> - trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
>> + trace_xics_ics_free_warn(0, i + ics->offset);
>
> Likewise here you should remove the always 0 parameter from the trace
> definition.
Sure.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-27 4:20 ` David Gibson
2016-06-27 4:56 ` Nikunj A Dadhania
@ 2016-06-27 4:59 ` Nikunj A Dadhania
1 sibling, 0 replies; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 4:59 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
>> static void xics_kvm_class_init(ObjectClass *oc, void *data)
>> diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c
>> index eda15a6..b03dd0d 100644
>> --- a/hw/intc/xics_spapr.c
>> +++ b/hw/intc/xics_spapr.c
>> @@ -113,10 +113,10 @@ static void rtas_set_xive(PowerPCCPU *cpu, sPAPRMachineState *spapr,
>> uint32_t nargs, target_ulong args,
>> uint32_t nret, target_ulong rets)
>> {
>> - ICSState *ics = spapr->xics->ics;
>> + ICSState *ics = QLIST_FIRST(&spapr->xics->ics);
>> uint32_t nr, server, priority;
>>
>> - if ((nargs != 3) || (nret != 1)) {
>> + if ((nargs != 3) || (nret != 1) || !ics) {
>> rtas_st(rets, 0, RTAS_OUT_PARAM_ERROR);
>> return;
>
> !ice should surely be an assert, or at least a HW_ERROR, not a PARAM_ERROR.
Sure, will make those changes
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-27 4:26 ` David Gibson
@ 2016-06-27 5:18 ` Nikunj A Dadhania
2016-06-27 10:11 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 5:18 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> The existing implementation remains same and ics-base is introduced.
>>
>> This will allow different implementations for the source controllers
>> such as the MSI support of PHB3 on Power8 which uses in-memory state
>> tables for example.
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
>> hw/intc/xics_spapr.c | 36 ++++++++++--------
>> include/hw/ppc/xics.h | 11 +++++-
>> 3 files changed, 97 insertions(+), 51 deletions(-)
>>
>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> index 326d21f..e2aa48d 100644
>> --- a/hw/intc/xics.c
>> +++ b/hw/intc/xics.c
>> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
>> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
>> #define CPPR(ss) (((ss)->xirr) >> 24)
>>
>> -static void ics_reject(ICSState *ics, int nr);
>> -static void ics_resend(ICSState *ics);
>> -static void ics_eoi(ICSState *ics, int nr);
>> +static void ics_base_reject(ICSState *ics, uint32_t nr)
>
> AFICT these will actually work for any of the derived classes, since
> they call the function pointer. So I thin the original name was
> better than ics_base_*().
Sure, will change.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-27 4:56 ` Nikunj A Dadhania
@ 2016-06-27 5:30 ` David Gibson
2016-06-27 5:32 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-27 5:30 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 4939 bytes --]
On Mon, Jun 27, 2016 at 10:26:42AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Thu, Jun 23, 2016 at 11:17:25PM +0530, Nikunj A Dadhania wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> Instead of an array of fixed sized blocks, use a list, as we will need
> >> to have sources with variable number of interrupts. SPAPR only uses
> >> a single entry. Native will create more. If performance becomes an
> >> issue we can add some hashed lookup but for now this will do fine.
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> hw/intc/xics.c | 78 +++++++++++++++++++++++++++---------------------
> >> hw/intc/xics_kvm.c | 29 +++++++++++++-----
> >> hw/intc/xics_spapr.c | 82 +++++++++++++++++++++++++++++----------------------
> >> hw/ppc/spapr_events.c | 2 +-
> >> hw/ppc/spapr_pci.c | 5 ++--
> >> hw/ppc/spapr_vio.c | 2 +-
> >> include/hw/ppc/xics.h | 13 ++++----
> >> 7 files changed, 124 insertions(+), 87 deletions(-)
> >>
> >> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> >> index 38e51fc..ef2a1e4 100644
> >> --- a/hw/intc/xics.c
> >> +++ b/hw/intc/xics.c
> >> @@ -96,13 +96,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
> >> static void xics_common_reset(DeviceState *d)
> >> {
> >> XICSState *xics = XICS_COMMON(d);
> >> + ICSState *ics;
> >> int i;
> >>
> >> for (i = 0; i < xics->nr_servers; i++) {
> >> device_reset(DEVICE(&xics->ss[i]));
> >> }
> >>
> >> - device_reset(DEVICE(xics->ics));
> >> + QLIST_FOREACH(ics, &xics->ics, list) {
> >> + device_reset(DEVICE(ics));
> >> + }
> >> }
> >>
> >> static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
> >> @@ -134,7 +137,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
> >> }
> >>
> >> assert(info->set_nr_irqs);
> >> - assert(xics->ics);
> >> info->set_nr_irqs(xics, value, errp);
> >> }
> >>
> >> @@ -212,33 +214,35 @@ static void ics_reject(ICSState *ics, int nr);
> >> static void ics_resend(ICSState *ics);
> >> static void ics_eoi(ICSState *ics, int nr);
> >>
> >> -static void icp_check_ipi(XICSState *xics, int server)
> >> +static void icp_check_ipi(ICPState *ss, int server)
> >
> > Since you're now passing ICPState, you don't need the server
> > parameter, since its only purpose is to locate the right ICPState in
> > the XICSState.
>
> Right, i had retained this as there was a trace function using it. Maybe
> we can then move the trace to the caller.
Or just change the trace template.
> >> @@ -361,13 +375,16 @@ int xics_spapr_alloc(XICSState *xics, int src, int irq_hint, bool lsi,
> >> * Allocate block of consecutive IRQs, and return the number of the first IRQ in
> >> * the block. If align==true, aligns the first IRQ number to num.
> >> */
> >> -int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
> >> - bool align, Error **errp)
> >> +int xics_spapr_alloc_block(XICSState *xics, int num, bool lsi, bool align,
> >> + Error **errp)
> >> {
> >> + ICSState *ics = QLIST_FIRST(&xics->ics);
> >> int i, first = -1;
> >> - ICSState *ics = &xics->ics[src];
> >
> > Ouch.. AFAICT this would have SEGVed if it was ever called with src != 0.
> >
> >>
> >> - assert(src == 0);
> >> + if (!ics) {
> >> + return -1;
> >> + }
> >> +
> >> /*
> >> * MSIMesage::data is used for storing VIRQ so
> >> * it has to be aligned to num to support multiple
> >> @@ -394,7 +411,7 @@ int xics_spapr_alloc_block(XICSState *xics, int src, int num, bool lsi,
> >> }
> >> first += ics->offset;
> >>
> >> - trace_xics_alloc_block(src, first, num, lsi, align);
> >> + trace_xics_alloc_block(0, first, num, lsi, align);
> >
> > You should remove the src from the trave definition since it has to be
> > 0.
>
> Sure.
>
> >>
> >> return first;
> >> }
> >> @@ -405,7 +422,7 @@ static void ics_free(ICSState *ics, int srcno, int num)
> >>
> >> for (i = srcno; i < srcno + num; ++i) {
> >> if (ICS_IRQ_FREE(ics, i)) {
> >> - trace_xics_ics_free_warn(ics - ics->xics->ics, i + ics->offset);
> >> + trace_xics_ics_free_warn(0, i + ics->offset);
> >
> > Likewise here you should remove the always 0 parameter from the trace
> > definition.
>
> Sure.
>
> Regards
> Nikunj
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list
2016-06-27 5:30 ` David Gibson
@ 2016-06-27 5:32 ` Nikunj A Dadhania
0 siblings, 0 replies; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 5:32 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Mon, Jun 27, 2016 at 10:26:42AM +0530, Nikunj A Dadhania wrote:
>> David Gibson <david@gibson.dropbear.id.au> writes:
>>
>> > [ Unknown signature status ]
>> > On Thu, Jun 23, 2016 at 11:17:25PM +0530, Nikunj A Dadhania wrote:
>> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> >>
>> >> Instead of an array of fixed sized blocks, use a list, as we will need
>> >> to have sources with variable number of interrupts. SPAPR only uses
>> >> a single entry. Native will create more. If performance becomes an
>> >> issue we can add some hashed lookup but for now this will do fine.
>> >>
>> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> >> ---
>> >> hw/intc/xics.c | 78 +++++++++++++++++++++++++++---------------------
>> >> hw/intc/xics_kvm.c | 29 +++++++++++++-----
>> >> hw/intc/xics_spapr.c | 82 +++++++++++++++++++++++++++++----------------------
>> >> hw/ppc/spapr_events.c | 2 +-
>> >> hw/ppc/spapr_pci.c | 5 ++--
>> >> hw/ppc/spapr_vio.c | 2 +-
>> >> include/hw/ppc/xics.h | 13 ++++----
>> >> 7 files changed, 124 insertions(+), 87 deletions(-)
>> >>
>> >> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> >> index 38e51fc..ef2a1e4 100644
>> >> --- a/hw/intc/xics.c
>> >> +++ b/hw/intc/xics.c
>> >> @@ -96,13 +96,16 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
>> >> static void xics_common_reset(DeviceState *d)
>> >> {
>> >> XICSState *xics = XICS_COMMON(d);
>> >> + ICSState *ics;
>> >> int i;
>> >>
>> >> for (i = 0; i < xics->nr_servers; i++) {
>> >> device_reset(DEVICE(&xics->ss[i]));
>> >> }
>> >>
>> >> - device_reset(DEVICE(xics->ics));
>> >> + QLIST_FOREACH(ics, &xics->ics, list) {
>> >> + device_reset(DEVICE(ics));
>> >> + }
>> >> }
>> >>
>> >> static void xics_prop_get_nr_irqs(Object *obj, Visitor *v, const char *name,
>> >> @@ -134,7 +137,6 @@ static void xics_prop_set_nr_irqs(Object *obj, Visitor *v, const char *name,
>> >> }
>> >>
>> >> assert(info->set_nr_irqs);
>> >> - assert(xics->ics);
>> >> info->set_nr_irqs(xics, value, errp);
>> >> }
>> >>
>> >> @@ -212,33 +214,35 @@ static void ics_reject(ICSState *ics, int nr);
>> >> static void ics_resend(ICSState *ics);
>> >> static void ics_eoi(ICSState *ics, int nr);
>> >>
>> >> -static void icp_check_ipi(XICSState *xics, int server)
>> >> +static void icp_check_ipi(ICPState *ss, int server)
>> >
>> > Since you're now passing ICPState, you don't need the server
>> > parameter, since its only purpose is to locate the right ICPState in
>> > the XICSState.
>>
>> Right, i had retained this as there was a trace function using it. Maybe
>> we can then move the trace to the caller.
>
> Or just change the trace template.
Sure.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command
2016-06-27 4:48 ` David Gibson
@ 2016-06-27 5:56 ` Benjamin Herrenschmidt
0 siblings, 0 replies; 37+ messages in thread
From: Benjamin Herrenschmidt @ 2016-06-27 5:56 UTC (permalink / raw)
To: David Gibson, Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg
On Mon, 2016-06-27 at 14:48 +1000, David Gibson wrote:
> I'm a bit dubious about this, since I'm not sure info pic really has
> much purpose at all. I posted a patch a while back to remove it
> entirely, but it didn't go far for lack of interested, and so far I
> didn't get time to revisit it and try pushing.
It has been useful to me when I was debugging that stuff...
Cheers,
Ben.
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass
2016-06-27 4:36 ` David Gibson
@ 2016-06-27 9:53 ` Nikunj A Dadhania
2016-06-28 2:58 ` David Gibson
0 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 9:53 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Thu, Jun 23, 2016 at 11:17:29PM +0530, Nikunj A Dadhania wrote:
>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>
>> This provides MMIO based ICP access as found on POWER8
>>
>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> default-configs/ppc64-softmmu.mak | 3 +-
>> hw/intc/Makefile.objs | 1 +
>> hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++++++++
>> include/hw/ppc/xics.h | 14 ++
>> 4 files changed, 312 insertions(+), 1 deletion(-)
>> create mode 100644 hw/intc/xics_native.c
>>
>> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
>> index c4be59f..315e30b 100644
>> --- a/default-configs/ppc64-softmmu.mak
>> +++ b/default-configs/ppc64-softmmu.mak
>> @@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=y
>> CONFIG_ETSEC=y
>> CONFIG_LIBDECNUMBER=y
>> # For pSeries
>> -CONFIG_XICS=$(CONFIG_PSERIES)
>> +CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV))
>> CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
>> +CONFIG_XICS_NATIVE=$(CONFIG_POWERNV)
>> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
>
> I don't think you've introduced CONFIG_POWERNV in your patches so far,
> making this a bit weird.
I had kept this patch for completeness and review. We can push this once
the POWERNV bits trickles in.
>
>> # For PReP
>> CONFIG_MC146818RTC=y
>> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
>> index 530df2e..f8bbeda 100644
>> --- a/hw/intc/Makefile.objs
>> +++ b/hw/intc/Makefile.objs
>> @@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
>> obj-$(CONFIG_SH4) += sh_intc.o
>> obj-$(CONFIG_XICS) += xics.o
>> obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
>> +obj-$(CONFIG_XICS_NATIVE) += xics_native.o
>> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
>> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
>> obj-$(CONFIG_S390_FLIC) += s390_flic.o
>> diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c
>> new file mode 100644
>> index 0000000..26e45cc
>> --- /dev/null
>> +++ b/hw/intc/xics_native.c
>> @@ -0,0 +1,295 @@
>> +/*
>> + * QEMU PowerPC hardware System Emulator
>> + *
>> + * Native version of ICS/ICP
>> + *
>> + * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
>
> Surely this should have yours or Ben's copyright in addition to mine.
Sure, will add Ben's copyright.
>> + * Permission is hereby granted, free of charge, to any person obtaining a copy
>> + * of this software and associated documentation files (the "Software"), to deal
>> + * in the Software without restriction, including without limitation the rights
>> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
>> + * copies of the Software, and to permit persons to whom the Software is
>> + * furnished to do so, subject to the following conditions:
>> + *
>> + * The above copyright notice and this permission notice shall be included in
>> + * all copies or substantial portions of the Software.
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
>> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
>> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
>> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
>> + * THE SOFTWARE.
>> + *
>> + */
>> +
>> +#include "qemu/osdep.h"
>> +#include "hw/hw.h"
>> +#include "trace.h"
>> +#include "qemu/timer.h"
>> +#include "hw/ppc/xics.h"
>> +#include "qapi/visitor.h"
>> +#include "qapi/error.h"
>> +
>> +#include <libfdt.h>
>> +
>> +/* #define DEBUG_MM(fmt...) printf(fmt) */
>> +#define DEBUG_MM(fmt...) do { } while (0)
>> +
>> +static void xics_native_initfn(Object *obj)
>> +{
>> + XICSState *xics = XICS_NATIVE(obj);
>> +
>> + QLIST_INIT(&xics->ics);
>> +}
>> +
>> +static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width)
>> +{
>> + XICSState *s = opaque;
>> + int32_t cpu_id, server;
>> + uint32_t val;
>> + ICPState *ss;
>> + bool byte0 = (width == 1 && (addr & 0x3) == 0);
>> +
>> + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
>> + server = get_cpu_index_by_dt_id(cpu_id);
>
> Shouldn't each ICP instance register its own MMIO window?
That is how the hardware works. Moreover, there is an SCOM that controls
ICP BAR. We might support moving the ICP BAR at some stage so I'd rather
keep it consistent.
[...]
>> +
>> +#define _FDT(exp) \
>> + do { \
>> + int ret = (exp); \
>> + if (ret < 0) { \
>> + fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
>> + #exp, fdt_strerror(ret)); \
>> + exit(1); \
>> + } \
>> + } while (0)
>
> Ugh, I have got to find time to push by qdt cleanup stuff again.
Yes, those are nice set of patches.
> Not within scope for this patch obviously, though.
>
>>
>> #define XICS_IPI 0x2
>> #define XICS_BUID 0x1
>> @@ -84,6 +89,7 @@ struct XICSState {
>> uint32_t nr_irqs;
>> ICPState *ss;
>> QLIST_HEAD(, ICSState) ics;
>> + MemoryRegion icp_mmio;
>
> This is only used by XICSNative, so it should be in a structure just
> for the subclass, not in the common struct.
Sure.
>> };
>>
>> #define TYPE_ICP "icp"
>> @@ -115,8 +121,13 @@ struct ICPState {
>> uint8_t mfrr;
>> qemu_irq output;
>> bool cap_irq_xics_enabled;
>> + uint32_t links[3];
>
> Likewise here.
Ok.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-27 5:18 ` Nikunj A Dadhania
@ 2016-06-27 10:11 ` Nikunj A Dadhania
2016-06-28 3:00 ` David Gibson
0 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-27 10:11 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
>> [ Unknown signature status ]
>> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
>>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>>
>>> The existing implementation remains same and ics-base is introduced.
>>>
>>> This will allow different implementations for the source controllers
>>> such as the MSI support of PHB3 on Power8 which uses in-memory state
>>> tables for example.
>>>
>>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>>> ---
>>> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
>>> hw/intc/xics_spapr.c | 36 ++++++++++--------
>>> include/hw/ppc/xics.h | 11 +++++-
>>> 3 files changed, 97 insertions(+), 51 deletions(-)
>>>
>>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>>> index 326d21f..e2aa48d 100644
>>> --- a/hw/intc/xics.c
>>> +++ b/hw/intc/xics.c
>>> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
>>> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
>>> #define CPPR(ss) (((ss)->xirr) >> 24)
>>>
>>> -static void ics_reject(ICSState *ics, int nr);
>>> -static void ics_resend(ICSState *ics);
>>> -static void ics_eoi(ICSState *ics, int nr);
>>> +static void ics_base_reject(ICSState *ics, uint32_t nr)
>>
>> AFICT these will actually work for any of the derived classes, since
>> they call the function pointer. So I thin the original name was
>> better than ics_base_*().
>
> Sure, will change.
I had a look at this again, we will need to use ics_base_*(), same file
has the implementation of ics_reject() for TYPE_ICS.
BenH's patches had renamed the class implementation as ics_simple_*().
Since we moved to using ICS_BASE, ICS and KVM_ICS, IMHO this seems to
the appropriate names.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass
2016-06-27 9:53 ` Nikunj A Dadhania
@ 2016-06-28 2:58 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-28 2:58 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 6798 bytes --]
On Mon, Jun 27, 2016 at 03:23:13PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Thu, Jun 23, 2016 at 11:17:29PM +0530, Nikunj A Dadhania wrote:
> >> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>
> >> This provides MMIO based ICP access as found on POWER8
> >>
> >> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> default-configs/ppc64-softmmu.mak | 3 +-
> >> hw/intc/Makefile.objs | 1 +
> >> hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++++++++
> >> include/hw/ppc/xics.h | 14 ++
> >> 4 files changed, 312 insertions(+), 1 deletion(-)
> >> create mode 100644 hw/intc/xics_native.c
> >>
> >> diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-softmmu.mak
> >> index c4be59f..315e30b 100644
> >> --- a/default-configs/ppc64-softmmu.mak
> >> +++ b/default-configs/ppc64-softmmu.mak
> >> @@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=y
> >> CONFIG_ETSEC=y
> >> CONFIG_LIBDECNUMBER=y
> >> # For pSeries
> >> -CONFIG_XICS=$(CONFIG_PSERIES)
> >> +CONFIG_XICS=$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV))
> >> CONFIG_XICS_SPAPR=$(CONFIG_PSERIES)
> >> +CONFIG_XICS_NATIVE=$(CONFIG_POWERNV)
> >> CONFIG_XICS_KVM=$(and $(CONFIG_PSERIES),$(CONFIG_KVM))
> >
> > I don't think you've introduced CONFIG_POWERNV in your patches so far,
> > making this a bit weird.
>
> I had kept this patch for completeness and review. We can push this once
> the POWERNV bits trickles in.
>
> >
> >> # For PReP
> >> CONFIG_MC146818RTC=y
> >> diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs
> >> index 530df2e..f8bbeda 100644
> >> --- a/hw/intc/Makefile.objs
> >> +++ b/hw/intc/Makefile.objs
> >> @@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) += bcm2835_ic.o bcm2836_control.o
> >> obj-$(CONFIG_SH4) += sh_intc.o
> >> obj-$(CONFIG_XICS) += xics.o
> >> obj-$(CONFIG_XICS_SPAPR) += xics_spapr.o
> >> +obj-$(CONFIG_XICS_NATIVE) += xics_native.o
> >> obj-$(CONFIG_XICS_KVM) += xics_kvm.o
> >> obj-$(CONFIG_ALLWINNER_A10_PIC) += allwinner-a10-pic.o
> >> obj-$(CONFIG_S390_FLIC) += s390_flic.o
> >> diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c
> >> new file mode 100644
> >> index 0000000..26e45cc
> >> --- /dev/null
> >> +++ b/hw/intc/xics_native.c
> >> @@ -0,0 +1,295 @@
> >> +/*
> >> + * QEMU PowerPC hardware System Emulator
> >> + *
> >> + * Native version of ICS/ICP
> >> + *
> >> + * Copyright (c) 2010,2011 David Gibson, IBM Corporation.
> >
> > Surely this should have yours or Ben's copyright in addition to mine.
>
> Sure, will add Ben's copyright.
>
> >> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> >> + * of this software and associated documentation files (the "Software"), to deal
> >> + * in the Software without restriction, including without limitation the rights
> >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> >> + * copies of the Software, and to permit persons to whom the Software is
> >> + * furnished to do so, subject to the following conditions:
> >> + *
> >> + * The above copyright notice and this permission notice shall be included in
> >> + * all copies or substantial portions of the Software.
> >> + *
> >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> >> + * THE SOFTWARE.
> >> + *
> >> + */
> >> +
> >> +#include "qemu/osdep.h"
> >> +#include "hw/hw.h"
> >> +#include "trace.h"
> >> +#include "qemu/timer.h"
> >> +#include "hw/ppc/xics.h"
> >> +#include "qapi/visitor.h"
> >> +#include "qapi/error.h"
> >> +
> >> +#include <libfdt.h>
> >> +
> >> +/* #define DEBUG_MM(fmt...) printf(fmt) */
> >> +#define DEBUG_MM(fmt...) do { } while (0)
> >> +
> >> +static void xics_native_initfn(Object *obj)
> >> +{
> >> + XICSState *xics = XICS_NATIVE(obj);
> >> +
> >> + QLIST_INIT(&xics->ics);
> >> +}
> >> +
> >> +static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width)
> >> +{
> >> + XICSState *s = opaque;
> >> + int32_t cpu_id, server;
> >> + uint32_t val;
> >> + ICPState *ss;
> >> + bool byte0 = (width == 1 && (addr & 0x3) == 0);
> >> +
> >> + cpu_id = (addr & (ICP_MM_SIZE - 1)) >> 12;
> >> + server = get_cpu_index_by_dt_id(cpu_id);
> >
> > Shouldn't each ICP instance register its own MMIO window?
>
> That is how the hardware works. Moreover, there is an SCOM that controls
> ICP BAR. We might support moving the ICP BAR at some stage so I'd rather
> keep it consistent.
Ok.
>
> [...]
>
> >> +
> >> +#define _FDT(exp) \
> >> + do { \
> >> + int ret = (exp); \
> >> + if (ret < 0) { \
> >> + fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
> >> + #exp, fdt_strerror(ret)); \
> >> + exit(1); \
> >> + } \
> >> + } while (0)
> >
> > Ugh, I have got to find time to push by qdt cleanup stuff again.
>
> Yes, those are nice set of patches.
>
> > Not within scope for this patch obviously, though.
> >
> >>
> >> #define XICS_IPI 0x2
> >> #define XICS_BUID 0x1
> >> @@ -84,6 +89,7 @@ struct XICSState {
> >> uint32_t nr_irqs;
> >> ICPState *ss;
> >> QLIST_HEAD(, ICSState) ics;
> >> + MemoryRegion icp_mmio;
> >
> > This is only used by XICSNative, so it should be in a structure just
> > for the subclass, not in the common struct.
>
> Sure.
>
> >> };
> >>
> >> #define TYPE_ICP "icp"
> >> @@ -115,8 +121,13 @@ struct ICPState {
> >> uint8_t mfrr;
> >> qemu_irq output;
> >> bool cap_irq_xics_enabled;
> >> + uint32_t links[3];
> >
> > Likewise here.
>
> Ok.
>
> Regards
> Nikunj
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-27 10:11 ` Nikunj A Dadhania
@ 2016-06-28 3:00 ` David Gibson
2016-06-28 5:06 ` Nikunj A Dadhania
0 siblings, 1 reply; 37+ messages in thread
From: David Gibson @ 2016-06-28 3:00 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 2705 bytes --]
On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
> Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes:
>
> > David Gibson <david@gibson.dropbear.id.au> writes:
> >
> >> [ Unknown signature status ]
> >> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
> >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>>
> >>> The existing implementation remains same and ics-base is introduced.
> >>>
> >>> This will allow different implementations for the source controllers
> >>> such as the MSI support of PHB3 on Power8 which uses in-memory state
> >>> tables for example.
> >>>
> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >>> ---
> >>> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
> >>> hw/intc/xics_spapr.c | 36 ++++++++++--------
> >>> include/hw/ppc/xics.h | 11 +++++-
> >>> 3 files changed, 97 insertions(+), 51 deletions(-)
> >>>
> >>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> >>> index 326d21f..e2aa48d 100644
> >>> --- a/hw/intc/xics.c
> >>> +++ b/hw/intc/xics.c
> >>> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
> >>> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
> >>> #define CPPR(ss) (((ss)->xirr) >> 24)
> >>>
> >>> -static void ics_reject(ICSState *ics, int nr);
> >>> -static void ics_resend(ICSState *ics);
> >>> -static void ics_eoi(ICSState *ics, int nr);
> >>> +static void ics_base_reject(ICSState *ics, uint32_t nr)
> >>
> >> AFICT these will actually work for any of the derived classes, since
> >> they call the function pointer. So I thin the original name was
> >> better than ics_base_*().
> >
> > Sure, will change.
>
> I had a look at this again, we will need to use ics_base_*(), same file
> has the implementation of ics_reject() for TYPE_ICS.
No, the ics_reject() plain names still work best for the generic
versions which call via the function pointers. Instead we should find
a new name for the TYPE_ICE implementations.
> BenH's patches had renamed the class implementation as ics_simple_*().
> Since we moved to using ICS_BASE, ICS and KVM_ICS, IMHO this seems to
> the appropriate names.
No. Using ics_base_*() for the generic versions is actively
misleading. Using good names for those is more important than what
would usually be consistent naming practice for the TYPE_ICS
implementation.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-28 3:00 ` David Gibson
@ 2016-06-28 5:06 ` Nikunj A Dadhania
2016-06-28 6:25 ` David Gibson
0 siblings, 1 reply; 37+ messages in thread
From: Nikunj A Dadhania @ 2016-06-28 5:06 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
>> Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes:
>>
>> > David Gibson <david@gibson.dropbear.id.au> writes:
>> >
>> >> [ Unknown signature status ]
>> >> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
>> >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> >>>
>> >>> The existing implementation remains same and ics-base is introduced.
>> >>>
>> >>> This will allow different implementations for the source controllers
>> >>> such as the MSI support of PHB3 on Power8 which uses in-memory state
>> >>> tables for example.
>> >>>
>> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
>> >>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> >>> ---
>> >>> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
>> >>> hw/intc/xics_spapr.c | 36 ++++++++++--------
>> >>> include/hw/ppc/xics.h | 11 +++++-
>> >>> 3 files changed, 97 insertions(+), 51 deletions(-)
>> >>>
>> >>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> >>> index 326d21f..e2aa48d 100644
>> >>> --- a/hw/intc/xics.c
>> >>> +++ b/hw/intc/xics.c
>> >>> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
>> >>> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
>> >>> #define CPPR(ss) (((ss)->xirr) >> 24)
>> >>>
>> >>> -static void ics_reject(ICSState *ics, int nr);
>> >>> -static void ics_resend(ICSState *ics);
>> >>> -static void ics_eoi(ICSState *ics, int nr);
>> >>> +static void ics_base_reject(ICSState *ics, uint32_t nr)
>> >>
>> >> AFICT these will actually work for any of the derived classes, since
>> >> they call the function pointer. So I thin the original name was
>> >> better than ics_base_*().
>> >
>> > Sure, will change.
>>
>> I had a look at this again, we will need to use ics_base_*(), same file
>> has the implementation of ics_reject() for TYPE_ICS.
>
> No, the ics_reject() plain names still work best for the generic
> versions which call via the function pointers. Instead we should find
> a new name for the TYPE_ICE implementations.
Should we go back to call it as TYPE_ICS_SIMPLE retaining the "ics" for
migration compatibility. Rename all the related functions as
ics_simple_*
Similar to what we did for XICS
#define TYPE_XICS_COMMON "xics-common"
#define TYPE_XICS_SPAPR "xics"
#define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
#define TYPE_XICS_NATIVE "xics-native"
Like this
#define TYPE_ICS_BASE "ics-base"
#define TYPE_ICS_SIMPLE "ics"
#define TYPE_KVM_ICS "icskvm"
>
>> BenH's patches had renamed the class implementation as ics_simple_*().
>> Since we moved to using ICS_BASE, ICS and KVM_ICS, IMHO this seems to
>> the appropriate names.
>
> No. Using ics_base_*() for the generic versions is actively
> misleading. Using good names for those is more important than what
> would usually be consistent naming practice for the TYPE_ICS
> implementation.
Regards
Nikunj
^ permalink raw reply [flat|nested] 37+ messages in thread
* Re: [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class
2016-06-28 5:06 ` Nikunj A Dadhania
@ 2016-06-28 6:25 ` David Gibson
0 siblings, 0 replies; 37+ messages in thread
From: David Gibson @ 2016-06-28 6:25 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, qemu-devel, clg, Benjamin Herrenschmidt
[-- Attachment #1: Type: text/plain, Size: 3608 bytes --]
On Tue, Jun 28, 2016 at 10:36:23AM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Mon, Jun 27, 2016 at 03:41:06PM +0530, Nikunj A Dadhania wrote:
> >> Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> writes:
> >>
> >> > David Gibson <david@gibson.dropbear.id.au> writes:
> >> >
> >> >> [ Unknown signature status ]
> >> >> On Thu, Jun 23, 2016 at 11:17:28PM +0530, Nikunj A Dadhania wrote:
> >> >>> From: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> >>>
> >> >>> The existing implementation remains same and ics-base is introduced.
> >> >>>
> >> >>> This will allow different implementations for the source controllers
> >> >>> such as the MSI support of PHB3 on Power8 which uses in-memory state
> >> >>> tables for example.
> >> >>>
> >> >>> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
> >> >>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> >>> ---
> >> >>> hw/intc/xics.c | 101 +++++++++++++++++++++++++++++++++-----------------
> >> >>> hw/intc/xics_spapr.c | 36 ++++++++++--------
> >> >>> include/hw/ppc/xics.h | 11 +++++-
> >> >>> 3 files changed, 97 insertions(+), 51 deletions(-)
> >> >>>
> >> >>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> >> >>> index 326d21f..e2aa48d 100644
> >> >>> --- a/hw/intc/xics.c
> >> >>> +++ b/hw/intc/xics.c
> >> >>> @@ -220,9 +220,32 @@ static const TypeInfo xics_common_info = {
> >> >>> #define XISR(ss) (((ss)->xirr) & XISR_MASK)
> >> >>> #define CPPR(ss) (((ss)->xirr) >> 24)
> >> >>>
> >> >>> -static void ics_reject(ICSState *ics, int nr);
> >> >>> -static void ics_resend(ICSState *ics);
> >> >>> -static void ics_eoi(ICSState *ics, int nr);
> >> >>> +static void ics_base_reject(ICSState *ics, uint32_t nr)
> >> >>
> >> >> AFICT these will actually work for any of the derived classes, since
> >> >> they call the function pointer. So I thin the original name was
> >> >> better than ics_base_*().
> >> >
> >> > Sure, will change.
> >>
> >> I had a look at this again, we will need to use ics_base_*(), same file
> >> has the implementation of ics_reject() for TYPE_ICS.
> >
> > No, the ics_reject() plain names still work best for the generic
> > versions which call via the function pointers. Instead we should find
> > a new name for the TYPE_ICE implementations.
>
> Should we go back to call it as TYPE_ICS_SIMPLE retaining the "ics" for
> migration compatibility. Rename all the related functions as
> ics_simple_*
>
> Similar to what we did for XICS
>
> #define TYPE_XICS_COMMON "xics-common"
> #define TYPE_XICS_SPAPR "xics"
> #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm"
> #define TYPE_XICS_NATIVE "xics-native"
>
>
> Like this
>
>
> #define TYPE_ICS_BASE "ics-base"
> #define TYPE_ICS_SIMPLE "ics"
> #define TYPE_KVM_ICS "icskvm"
Yes, that would be ok with me.
> >> BenH's patches had renamed the class implementation as ics_simple_*().
> >> Since we moved to using ICS_BASE, ICS and KVM_ICS, IMHO this seems to
> >> the appropriate names.
> >
> > No. Using ics_base_*() for the generic versions is actively
> > misleading. Using good names for those is more important than what
> > would usually be consistent naming practice for the TYPE_ICS
> > implementation.
>
> Regards
> Nikunj
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 37+ messages in thread
end of thread, other threads:[~2016-06-28 6:33 UTC | newest]
Thread overview: 37+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2016-06-23 17:47 [Qemu-devel] [PATCH v1 00/11] sPAPR xics rework/cleanup Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 01/11] ppc/xics: Rename existing xics to xics_spapr Nikunj A Dadhania
2016-06-24 5:17 ` David Gibson
2016-06-24 5:53 ` Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 02/11] ppc/xics: Move SPAPR specific code to a separate file Nikunj A Dadhania
2016-06-24 5:19 ` David Gibson
2016-06-24 5:57 ` Nikunj A Dadhania
2016-06-24 6:12 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 03/11] ppc/xics: Implement H_IPOLL using an accessor Nikunj A Dadhania
2016-06-24 5:21 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 04/11] ppc/xics: Remove unused xics_set_irq_type() Nikunj A Dadhania
2016-06-24 5:45 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 05/11] ppc/xics: Replace "icp" with "xics" in most places Nikunj A Dadhania
2016-06-27 3:43 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 06/11] ppc/xics: Make the ICSState a list Nikunj A Dadhania
2016-06-27 4:20 ` David Gibson
2016-06-27 4:56 ` Nikunj A Dadhania
2016-06-27 5:30 ` David Gibson
2016-06-27 5:32 ` Nikunj A Dadhania
2016-06-27 4:59 ` Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 07/11] ppc/xics: An ICS with offset 0 is assumed to be uninitialized Nikunj A Dadhania
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 08/11] ppc/xics: Use a helper to add a new ICS Nikunj A Dadhania
2016-06-27 4:21 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 09/11] ppc/xics: Split ICS into ics-base and ics class Nikunj A Dadhania
2016-06-27 4:26 ` David Gibson
2016-06-27 5:18 ` Nikunj A Dadhania
2016-06-27 10:11 ` Nikunj A Dadhania
2016-06-28 3:00 ` David Gibson
2016-06-28 5:06 ` Nikunj A Dadhania
2016-06-28 6:25 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass Nikunj A Dadhania
2016-06-27 4:36 ` David Gibson
2016-06-27 9:53 ` Nikunj A Dadhania
2016-06-28 2:58 ` David Gibson
2016-06-23 17:47 ` [Qemu-devel] [PATCH v1 11/11] ppc/xics: Add xics to the monitor "info pic" command Nikunj A Dadhania
2016-06-27 4:48 ` David Gibson
2016-06-27 5:56 ` Benjamin Herrenschmidt
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