From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56859) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHOSL-0006UE-3h for qemu-devel@nongnu.org; Mon, 27 Jun 2016 00:47:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHOSI-0001wG-2h for qemu-devel@nongnu.org; Mon, 27 Jun 2016 00:47:33 -0400 Date: Mon, 27 Jun 2016 14:36:45 +1000 From: David Gibson Message-ID: <20160627043645.GI4242@voom.fritz.box> References: <1466704050-15108-1-git-send-email-nikunj@linux.vnet.ibm.com> <1466704050-15108-11-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Rmm1Stw9KgbdL9/H" Content-Disposition: inline In-Reply-To: <1466704050-15108-11-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v1 10/11] ppc/xics: Add "native" XICS subclass List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, clg@kaod.org, Benjamin Herrenschmidt --Rmm1Stw9KgbdL9/H Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jun 23, 2016 at 11:17:29PM +0530, Nikunj A Dadhania wrote: > From: Benjamin Herrenschmidt >=20 > This provides MMIO based ICP access as found on POWER8 >=20 > Signed-off-by: Benjamin Herrenschmidt > Signed-off-by: Nikunj A Dadhania > --- > default-configs/ppc64-softmmu.mak | 3 +- > hw/intc/Makefile.objs | 1 + > hw/intc/xics_native.c | 295 ++++++++++++++++++++++++++++++++= ++++++ > include/hw/ppc/xics.h | 14 ++ > 4 files changed, 312 insertions(+), 1 deletion(-) > create mode 100644 hw/intc/xics_native.c >=20 > diff --git a/default-configs/ppc64-softmmu.mak b/default-configs/ppc64-so= ftmmu.mak > index c4be59f..315e30b 100644 > --- a/default-configs/ppc64-softmmu.mak > +++ b/default-configs/ppc64-softmmu.mak > @@ -48,8 +48,9 @@ CONFIG_PLATFORM_BUS=3Dy > CONFIG_ETSEC=3Dy > CONFIG_LIBDECNUMBER=3Dy > # For pSeries > -CONFIG_XICS=3D$(CONFIG_PSERIES) > +CONFIG_XICS=3D$(or $(CONFIG_PSERIES),$(CONFIG_POWERNV)) > CONFIG_XICS_SPAPR=3D$(CONFIG_PSERIES) > +CONFIG_XICS_NATIVE=3D$(CONFIG_POWERNV) > CONFIG_XICS_KVM=3D$(and $(CONFIG_PSERIES),$(CONFIG_KVM)) I don't think you've introduced CONFIG_POWERNV in your patches so far, making this a bit weird. > # For PReP > CONFIG_MC146818RTC=3Dy > diff --git a/hw/intc/Makefile.objs b/hw/intc/Makefile.objs > index 530df2e..f8bbeda 100644 > --- a/hw/intc/Makefile.objs > +++ b/hw/intc/Makefile.objs > @@ -31,6 +31,7 @@ obj-$(CONFIG_RASPI) +=3D bcm2835_ic.o bcm2836_control.o > obj-$(CONFIG_SH4) +=3D sh_intc.o > obj-$(CONFIG_XICS) +=3D xics.o > obj-$(CONFIG_XICS_SPAPR) +=3D xics_spapr.o > +obj-$(CONFIG_XICS_NATIVE) +=3D xics_native.o > obj-$(CONFIG_XICS_KVM) +=3D xics_kvm.o > obj-$(CONFIG_ALLWINNER_A10_PIC) +=3D allwinner-a10-pic.o > obj-$(CONFIG_S390_FLIC) +=3D s390_flic.o > diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c > new file mode 100644 > index 0000000..26e45cc > --- /dev/null > +++ b/hw/intc/xics_native.c > @@ -0,0 +1,295 @@ > +/* > + * QEMU PowerPC hardware System Emulator > + * > + * Native version of ICS/ICP > + * > + * Copyright (c) 2010,2011 David Gibson, IBM Corporation. Surely this should have yours or Ben's copyright in addition to mine. > + * Permission is hereby granted, free of charge, to any person obtaining= a copy > + * of this software and associated documentation files (the "Software"),= to deal > + * in the Software without restriction, including without limitation the= rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or = sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be includ= ed in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRE= SS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILI= TY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHA= LL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR = OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISI= NG FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALING= S IN > + * THE SOFTWARE. > + * > + */ > + > +#include "qemu/osdep.h" > +#include "hw/hw.h" > +#include "trace.h" > +#include "qemu/timer.h" > +#include "hw/ppc/xics.h" > +#include "qapi/visitor.h" > +#include "qapi/error.h" > + > +#include > + > +/* #define DEBUG_MM(fmt...) printf(fmt) */ > +#define DEBUG_MM(fmt...) do { } while (0) > + > +static void xics_native_initfn(Object *obj) > +{ > + XICSState *xics =3D XICS_NATIVE(obj); > + > + QLIST_INIT(&xics->ics); > +} > + > +static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width) > +{ > + XICSState *s =3D opaque; > + int32_t cpu_id, server; > + uint32_t val; > + ICPState *ss; > + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); > + > + cpu_id =3D (addr & (ICP_MM_SIZE - 1)) >> 12; > + server =3D get_cpu_index_by_dt_id(cpu_id); Shouldn't each ICP instance register its own MMIO window? > + if (server < 0) { > + fprintf(stderr, "XICS: Bad ICP server %d\n", server); > + goto bad_access; > + } > + ss =3D &s->ss[server]; > + switch (addr & 0xffc) { > + case 0: /* poll */ > + val =3D icp_ipoll(ss, NULL); > + if (byte0) { > + val >>=3D 24; > + } else if (width !=3D 4) { > + goto bad_access; > + } > + break; > + case 4: /* xirr */ > + if (byte0) { > + val =3D icp_ipoll(ss, NULL) >> 24; > + } else if (width =3D=3D 4) { > + val =3D icp_accept(ss); > + } else { > + goto bad_access; > + } > + break; > + case 12: > + if (byte0) { > + val =3D ss->mfrr; > + } else { > + goto bad_access; > + } > + break; > + case 16: > + if (width =3D=3D 4) { > + val =3D ss->links[0]; > + } else { > + goto bad_access; > + } > + break; > + case 20: > + if (width =3D=3D 4) { > + val =3D ss->links[1]; > + } else { > + goto bad_access; > + } > + break; > + case 24: > + if (width =3D=3D 4) { > + val =3D ss->links[2]; > + } else { > + goto bad_access; > + } > + break; > + default: > +bad_access: > + fprintf(stderr, "XICS: Bad ICP access %llx/%d\n", > + (unsigned long long)addr, width); > + val =3D 0xffffffff; > + } > + DEBUG_MM("icp_mm_read(addr=3D%016llx,serv=3D0x%x/%d,off=3D%d,w=3D%d,= val=3D0x%08x)\n", > + (unsigned long long)addr, cpu_id, server, (int)(addr & 0xff= c), > + width, val); > + > + return val; > +} > + > +static void icp_mm_write(void *opaque, hwaddr addr, uint64_t val, > + unsigned width) > +{ > + XICSState *s =3D opaque; > + int32_t cpu_id, server; > + ICPState *ss; > + bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); > + > + cpu_id =3D (addr & (ICP_MM_SIZE - 1)) >> 12; > + server =3D get_cpu_index_by_dt_id(cpu_id); > + if (server < 0) { > + fprintf(stderr, "XICS: Bad ICP server %d\n", server); > + goto bad_access; > + } > + ss =3D &s->ss[server]; > + > + DEBUG_MM("icp_mm_write(addr=3D%016llx,serv=3D0x%x/%d,off=3D%d,w=3D%d= ,val=3D0x%08x)\n", > + (unsigned long long)addr, cpu_id, server, > + (int)(addr & 0xffc), width, (uint32_t)val); > + > + switch (addr & 0xffc) { > + case 4: /* xirr */ > + if (byte0) { > + icp_set_cppr(s, server, val); > + } else if (width =3D=3D 4) { > + icp_eoi(s, server, val); > + } else { > + goto bad_access; > + } > + break; > + case 12: > + if (byte0) { > + icp_set_mfrr(s, server, val); > + } else { > + goto bad_access; > + } > + break; > + case 16: > + if (width =3D=3D 4) { > + ss->links[0] =3D val; > + } else { > + goto bad_access; > + } > + break; > + case 20: > + if (width =3D=3D 4) { > + ss->links[1] =3D val; > + } else { > + goto bad_access; > + } > + break; > + case 24: > + if (width =3D=3D 4) { > + ss->links[2] =3D val; > + } else { > + goto bad_access; > + } > + break; > + default: > + bad_access: > + val =3D 0xffffffff; > + } > +} > + > +static const MemoryRegionOps icp_mm_ops =3D { > + .read =3D icp_mm_read, > + .write =3D icp_mm_write, > + .valid.min_access_size =3D 1, > + .valid.max_access_size =3D 4, > + .impl.min_access_size =3D 1, > + .impl.max_access_size =3D 4, > + .endianness =3D DEVICE_BIG_ENDIAN, > +}; > + > +#define _FDT(exp) \ > + do { \ > + int ret =3D (exp); \ > + if (ret < 0) { \ > + fprintf(stderr, "qemu: error creating device tree: %s: %s\n"= , \ > + #exp, fdt_strerror(ret)); \ > + exit(1); \ > + } \ > + } while (0) Ugh, I have got to find time to push by qdt cleanup stuff again. Not within scope for this patch obviously, though. > +void xics_create_native_icp_node(XICSState *s, void *fdt, > + uint32_t base, uint32_t count) > +{ > + uint64_t addr; > + char *name; > + const char compat[] =3D "IBM,power8-icp\0IBM,ppc-xicp"; > + uint32_t irange[2], i, rsize; > + uint64_t *reg; > + > + addr =3D ICP_MM_BASE | (base << 12); > + > + irange[0] =3D cpu_to_be32(base); > + irange[1] =3D cpu_to_be32(count); > + > + rsize =3D sizeof(uint64_t) * 2 * count; > + reg =3D g_malloc(rsize); > + for (i =3D 0; i < count; i++) { > + reg[i * 2] =3D cpu_to_be64(addr | ((base + i) * 0x1000)); > + reg[i * 2 + 1] =3D cpu_to_be64(0x1000); > + } > + > + name =3D g_strdup_printf("interrupt-controller@%"PRIX64, addr); > + > + /* interrupt controller */ > + _FDT((fdt_begin_node(fdt, name))); > + g_free(name); > + > + _FDT((fdt_property(fdt, "compatible", compat, sizeof(compat)))); > + _FDT((fdt_property(fdt, "reg", reg, rsize))); > + _FDT((fdt_property_string(fdt, "device_type", > + "PowerPC-External-Interrupt-Presentation")= )); > + _FDT((fdt_property(fdt, "interrupt-controller", NULL, 0))); > + _FDT((fdt_property(fdt, "ibm,interrupt-server-ranges", > + irange, sizeof(irange)))); > + _FDT((fdt_property_cell(fdt, "#interrupt-cells", 1))); > + _FDT((fdt_property_cell(fdt, "#address-cells", 0))); > + _FDT((fdt_end_node(fdt))); > +} > + > +static void xics_native_realize(DeviceState *dev, Error **errp) > +{ > + XICSState *s =3D XICS_NATIVE(dev); > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > + Error *error =3D NULL; > + int i; > + > + if (!s->nr_servers) { > + error_setg(errp, "Number of servers needs to be greater 0"); > + return; > + } > + > + /* Register MMIO regions */ > + memory_region_init_io(&s->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp", > + ICP_MM_SIZE); > + sysbus_init_mmio(sbd, &s->icp_mmio); > + sysbus_mmio_map(sbd, 0, ICP_MM_BASE); > + > + for (i =3D 0; i < s->nr_servers; i++) { > + object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &e= rror); > + if (error) { > + error_propagate(errp, error); > + return; > + } > + } > +} > + > +static void xics_native_class_init(ObjectClass *oc, void *data) > +{ > + DeviceClass *dc =3D DEVICE_CLASS(oc); > + XICSStateClass *xsc =3D XICS_NATIVE_CLASS(oc); > + > + dc->realize =3D xics_native_realize; > + xsc->set_nr_servers =3D xics_set_nr_servers; > +} > + > +static const TypeInfo xics_native_info =3D { > + .name =3D TYPE_XICS_NATIVE, > + .parent =3D TYPE_XICS_COMMON, > + .instance_size =3D sizeof(XICSState), > + .class_size =3D sizeof(XICSStateClass), > + .class_init =3D xics_native_class_init, > + .instance_init =3D xics_native_initfn, > +}; > + > +static void xics_native_register_types(void) > +{ > + type_register_static(&xics_native_info); > +} > +type_init(xics_native_register_types) > diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h > index 6fb1cb4..0e47ecb 100644 > --- a/include/hw/ppc/xics.h > +++ b/include/hw/ppc/xics.h > @@ -42,6 +42,9 @@ > #define TYPE_XICS_SPAPR_KVM "xics-spapr-kvm" > #define KVM_XICS(obj) OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_= KVM) > =20 > +#define TYPE_XICS_NATIVE "xics-native" > +#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE) > + > #define XICS_COMMON_CLASS(klass) \ > OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) > #define XICS_SPAPR_CLASS(klass) \ > @@ -50,6 +53,8 @@ > OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_COMMON) > #define XICS_SPAPR_GET_CLASS(obj) \ > OBJECT_GET_CLASS(XICSStateClass, (obj), TYPE_XICS_SPAPR) > +#define XICS_NATIVE_CLASS(klass) \ > + OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_NATIVE) > =20 > #define XICS_IPI 0x2 > #define XICS_BUID 0x1 > @@ -84,6 +89,7 @@ struct XICSState { > uint32_t nr_irqs; > ICPState *ss; > QLIST_HEAD(, ICSState) ics; > + MemoryRegion icp_mmio; This is only used by XICSNative, so it should be in a structure just for the subclass, not in the common struct. > }; > =20 > #define TYPE_ICP "icp" > @@ -115,8 +121,13 @@ struct ICPState { > uint8_t mfrr; > qemu_irq output; > bool cap_irq_xics_enabled; > + uint32_t links[3]; Likewise here. > }; > =20 > +/* This should be an XSCOM BAR ... the size is arbitrary as well */ > +#define ICP_MM_BASE 0x0003FFFF80000000 > +#define ICP_MM_SIZE 0x0000000010000000 > + > #define TYPE_ICS_BASE "ics-base" > #define ICS_BASE(obj) OBJECT_CHECK(ICSState, (obj), TYPE_ICS_SIMPLE) > =20 > @@ -187,6 +198,9 @@ void xics_spapr_free(XICSState *icp, int irq, int num= ); > void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); > void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu); > =20 > +void xics_create_native_icp_node(XICSState *s, void *fdt, > + uint32_t base, uint32_t count); > + > /* Internal XICS interfaces */ > int get_cpu_index_by_dt_id(int cpu_dt_id); > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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