From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48591) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKA7j-0001fz-A0 for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:05:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bKA7e-00036N-T0 for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:05:42 -0400 Received: from mx1.redhat.com ([209.132.183.28]:54811) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKA7e-00036D-GH for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:05:38 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 277B2C049E1B for ; Mon, 4 Jul 2016 20:05:38 +0000 (UTC) Date: Mon, 4 Jul 2016 17:05:36 -0300 From: Eduardo Habkost Message-ID: <20160704200536.GG4131@thinpad.lan.raisama.net> References: <1467659769-15900-1-git-send-email-dgilbert@redhat.com> <1467659769-15900-3-git-send-email-dgilbert@redhat.com> <20160704230042-mutt-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160704230042-mutt-send-email-mst@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 2/6] x86: Mask mtrr mask based on CPU physical address limits List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: "Dr. David Alan Gilbert (git)" , qemu-devel@nongnu.org, pbonzini@redhat.com, marcel@redhat.com, kraxel@redhat.com On Mon, Jul 04, 2016 at 11:02:00PM +0300, Michael S. Tsirkin wrote: > On Mon, Jul 04, 2016 at 08:16:05PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > The CPU GPs if we try and set a bit in a variable MTRR mask above > > the limit of physical address bits on the host. We hit this > > when loading a migration from a host with a larger physical > > address limit than our destination (e.g. a Xeon->i7 of same > > generation) but previously used to get away with it > > until 48e1a45 started checking that msr writes actually worked. > > > > It seems in our case the GP probably comes from KVM emulating > > that GP. > > > > Signed-off-by: Dr. David Alan Gilbert > > Why don't we mask with host bits? This is the kvm limitation, > isn't it? This will make it possible to CC stable as well. KVM validates the value written to the MSR using the guest CPUID data, not the host bits. If we trim using the host bits, we would still crash if cpu->phys_bits < host_phys_bits. -- Eduardo