From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51910) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKANP-0004S6-5c for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:21:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bKANL-00066p-U0 for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:21:55 -0400 Received: from mx1.redhat.com ([209.132.183.28]:51338) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKANL-00066g-O0 for qemu-devel@nongnu.org; Mon, 04 Jul 2016 16:21:51 -0400 Received: from int-mx09.intmail.prod.int.phx2.redhat.com (int-mx09.intmail.prod.int.phx2.redhat.com [10.5.11.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 638F785543 for ; Mon, 4 Jul 2016 20:21:51 +0000 (UTC) Date: Mon, 4 Jul 2016 17:21:48 -0300 From: Eduardo Habkost Message-ID: <20160704202148.GI4131@thinpad.lan.raisama.net> References: <1467659769-15900-1-git-send-email-dgilbert@redhat.com> <1467659769-15900-4-git-send-email-dgilbert@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1467659769-15900-4-git-send-email-dgilbert@redhat.com> Subject: Re: [Qemu-devel] [PATCH v2 3/6] x86: fill high bits of mtrr mask List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Dr. David Alan Gilbert (git)" Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com On Mon, Jul 04, 2016 at 08:16:06PM +0100, Dr. David Alan Gilbert (git) wrote: [...] > @@ -2084,6 +2085,27 @@ static int kvm_get_msrs(X86CPU *cpu) > } > > assert(ret == cpu->kvm_msr_buf->nmsrs); > + /* > + * MTRR masks: Each mask consists of 5 parts > + * a 10..0: must be zero > + * b 11 : valid bit > + * c n-1.12: actual mask bits > + * d 51..n: reserved must be zero > + * e 63.52: reserved must be zero > + * > + * 'n' is the number of physical bits supported by the CPU and is > + * apparently always <= 52. We know our 'n' but don't know what > + * the destinations 'n' is; it might be smaller, in which case > + * it masks (c) on loading. It might be larger, in which case > + * we fill 'd' so that d..c is consistent irrespetive of the 'n' > + * we're migrating to. > + */ > + if (cpu->fill_mtrr_mask && cpu->phys_bits < 52) { > + mtrr_top_bits = MAKE_64BIT_MASK(cpu->phys_bits, 52 - cpu->phys_bits); > + } else { > + mtrr_top_bits = 0; How/where did you find this 52-bit limit? Is it documented somewhere? > + } > + > for (i = 0; i < ret; i++) { > uint32_t index = msrs[i].index; > switch (index) { > @@ -2279,7 +2301,8 @@ static int kvm_get_msrs(X86CPU *cpu) > break; > case MSR_MTRRphysBase(0) ... MSR_MTRRphysMask(MSR_MTRRcap_VCNT - 1): > if (index & 1) { > - env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data; > + env->mtrr_var[MSR_MTRRphysIndex(index)].mask = msrs[i].data | > + mtrr_top_bits; > } else { > env->mtrr_var[MSR_MTRRphysIndex(index)].base = msrs[i].data; > } > -- > 2.7.4 > -- Eduardo