From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54482) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bKxXr-0005ZH-6a for qemu-devel@nongnu.org; Wed, 06 Jul 2016 20:52:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bKxXo-0004jH-KI for qemu-devel@nongnu.org; Wed, 06 Jul 2016 20:51:58 -0400 Date: Thu, 7 Jul 2016 10:47:27 +1000 From: David Gibson Message-ID: <20160707004727.GB14675@voom.fritz.box> References: <1467795561-1007-1-git-send-email-bharata@linux.vnet.ibm.com> <1467795561-1007-2-git-send-email-bharata@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="oLBj+sq0vYjzfsbl" Content-Disposition: inline In-Reply-To: <1467795561-1007-2-git-send-email-bharata@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [RFC PATCH v1 1/5] cpu, target-ppc: Move cpu_vmstate_[un]register calls to cpu_common_[un]realize List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Bharata B Rao Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, imammedo@redhat.com, groug@kaod.org, nikunj@linux.vnet.ibm.com, pbonzini@redhat.com --oLBj+sq0vYjzfsbl Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jul 06, 2016 at 02:29:17PM +0530, Bharata B Rao wrote: > Move vmstate_register() call to cpu_common_realize(). > Introduce cpu_common_unrealize() and move vmstate_unregister() to it. >=20 > Change those archs that implement their own CPU unrealize routine to > mandatorily call CPUClass::unrealize(). >=20 > Signed-off-by: Bharata B Rao Reviewed-by: David Gibson > --- > exec.c | 53 ++++++++++++++++++++++++++++-----------= ------ > include/qom/cpu.h | 2 ++ > qom/cpu.c | 7 ++++++ > target-ppc/cpu-qom.h | 2 ++ > target-ppc/translate_init.c | 3 +++ > 5 files changed, 47 insertions(+), 20 deletions(-) >=20 > diff --git a/exec.c b/exec.c > index 0122ef7..fb73910 100644 > --- a/exec.c > +++ b/exec.c > @@ -594,9 +594,7 @@ AddressSpace *cpu_get_address_space(CPUState *cpu, in= t asidx) > /* Return the AddressSpace corresponding to the specified index */ > return cpu->cpu_ases[asidx].as; > } > -#endif > =20 > -#ifndef CONFIG_USER_ONLY > static DECLARE_BITMAP(cpu_index_map, MAX_CPUMASK_BITS); > =20 > static int cpu_get_free_index(Error **errp) > @@ -617,6 +615,31 @@ static void cpu_release_index(CPUState *cpu) > { > bitmap_clear(cpu_index_map, cpu->cpu_index, 1); > } > + > +void cpu_vmstate_register(CPUState *cpu) > +{ > + CPUClass *cc =3D CPU_GET_CLASS(cpu); > + > + if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { > + vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); > + } > + if (cc->vmsd !=3D NULL) { > + vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); > + } > +} > + > +void cpu_vmstate_unregister(CPUState *cpu) > +{ > + CPUClass *cc =3D CPU_GET_CLASS(cpu); > + > + if (cc->vmsd !=3D NULL) { > + vmstate_unregister(NULL, cc->vmsd, cpu); > + } > + if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { > + vmstate_unregister(NULL, &vmstate_cpu_common, cpu); > + } > +} > + > #else > =20 > static int cpu_get_free_index(Error **errp) > @@ -634,12 +657,18 @@ static void cpu_release_index(CPUState *cpu) > { > return; > } > + > +void cpu_vmstate_register(CPUState *cpu) > +{ > +} > + > +void cpu_vmstate_unregister(CPUState *cpu) > +{ > +} > #endif > =20 > void cpu_exec_exit(CPUState *cpu) > { > - CPUClass *cc =3D CPU_GET_CLASS(cpu); > - > #if defined(CONFIG_USER_ONLY) > cpu_list_lock(); > #endif > @@ -657,18 +686,10 @@ void cpu_exec_exit(CPUState *cpu) > #if defined(CONFIG_USER_ONLY) > cpu_list_unlock(); > #endif > - > - if (cc->vmsd !=3D NULL) { > - vmstate_unregister(NULL, cc->vmsd, cpu); > - } > - if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { > - vmstate_unregister(NULL, &vmstate_cpu_common, cpu); > - } > } > =20 > void cpu_exec_init(CPUState *cpu, Error **errp) > { > - CPUClass *cc =3D CPU_GET_CLASS(cpu); > Error *local_err =3D NULL; > =20 > cpu->as =3D NULL; > @@ -705,15 +726,7 @@ void cpu_exec_init(CPUState *cpu, Error **errp) > } > QTAILQ_INSERT_TAIL(&cpus, cpu, node); > #if defined(CONFIG_USER_ONLY) > - (void) cc; > cpu_list_unlock(); > -#else > - if (qdev_get_vmsd(DEVICE(cpu)) =3D=3D NULL) { > - vmstate_register(NULL, cpu->cpu_index, &vmstate_cpu_common, cpu); > - } > - if (cc->vmsd !=3D NULL) { > - vmstate_register(NULL, cpu->cpu_index, cc->vmsd, cpu); > - } > #endif > } > =20 > diff --git a/include/qom/cpu.h b/include/qom/cpu.h > index 32f3af3..29ccf5c 100644 > --- a/include/qom/cpu.h > +++ b/include/qom/cpu.h > @@ -870,4 +870,6 @@ extern const struct VMStateDescription vmstate_cpu_co= mmon; > .offset =3D 0, = \ > } > =20 > +void cpu_vmstate_register(CPUState *cpu); > +void cpu_vmstate_unregister(CPUState *cpu); > #endif > diff --git a/qom/cpu.c b/qom/cpu.c > index 751e992..488ecc6 100644 > --- a/qom/cpu.c > +++ b/qom/cpu.c > @@ -310,10 +310,16 @@ static void cpu_common_parse_features(CPUState *cpu= , char *features, > } > } > =20 > +static void cpu_common_unrealizefn(DeviceState *dev, Error **errp) > +{ > + cpu_vmstate_unregister(CPU(dev)); > +} > + > static void cpu_common_realizefn(DeviceState *dev, Error **errp) > { > CPUState *cpu =3D CPU(dev); > =20 > + cpu_vmstate_register(cpu); > if (dev->hotplugged) { > cpu_synchronize_post_init(cpu); > cpu_resume(cpu); > @@ -367,6 +373,7 @@ static void cpu_class_init(ObjectClass *klass, void *= data) > k->cpu_exec_exit =3D cpu_common_noop; > k->cpu_exec_interrupt =3D cpu_common_exec_interrupt; > dc->realize =3D cpu_common_realizefn; > + dc->unrealize =3D cpu_common_unrealizefn; > /* > * Reason: CPUs still need special care by board code: wiring up > * IRQs, adding reset handlers, halting non-first CPUs, ... > diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h > index 2864105..6ec2fca 100644 > --- a/target-ppc/cpu-qom.h > +++ b/target-ppc/cpu-qom.h > @@ -163,6 +163,7 @@ struct ppc_segment_page_sizes; > /** > * PowerPCCPUClass: > * @parent_realize: The parent class' realize handler. > + * @parent_unrealize: The parent class' unrealize handler. > * @parent_reset: The parent class' reset handler. > * > * A PowerPC CPU model. > @@ -173,6 +174,7 @@ typedef struct PowerPCCPUClass { > /*< public >*/ > =20 > DeviceRealize parent_realize; > + DeviceUnrealize parent_unrealize; > void (*parent_reset)(CPUState *cpu); > =20 > uint32_t pvr; > diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c > index 8f257fb..efd6b88 100644 > --- a/target-ppc/translate_init.c > +++ b/target-ppc/translate_init.c > @@ -9773,10 +9773,12 @@ static void ppc_cpu_realizefn(DeviceState *dev, E= rror **errp) > static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp) > { > PowerPCCPU *cpu =3D POWERPC_CPU(dev); > + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cpu); > CPUPPCState *env =3D &cpu->env; > opc_handler_t **table; > int i, j; > =20 > + pcc->parent_unrealize(dev, errp); > cpu_exec_exit(CPU(dev)); > =20 > for (i =3D 0; i < PPC_CPU_OPCODES_LEN; i++) { > @@ -10364,6 +10366,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, v= oid *data) > DeviceClass *dc =3D DEVICE_CLASS(oc); > =20 > pcc->parent_realize =3D dc->realize; > + pcc->parent_unrealize =3D dc->unrealize; > pcc->pvr_match =3D ppc_pvr_match_default; > pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; > dc->realize =3D ppc_cpu_realizefn; --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --oLBj+sq0vYjzfsbl Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXfaafAAoJEGw4ysog2bOSrH0QALLrFpi8HV/uVCYOxZlTb0W8 TGxuHE1hh1V6NYnE/645SuHQr5pgTgtxZP78iyltSXH7sz6kC342qQr2xsE5G/mE gxvSSqZExW/Yoz+SS1u5gQosEsfKZ8z0uY6kitr47uU3hwW0RsWqM560LzZbr4kD 6Zg+BFs3l+LbaMJ1IIY5uy/UMCIDhV80+rh+D0WU8t9KXkxm3tpjC6M2UW0CQYku mFWtpfI7t1CyMdiTuWN0zYdDbobSQ2gkk3A3JR4fty/VkpCEWRUopXa82+gx66ob ybOv6q46tG7LYrzY6jNUOsr3icoAw8bIXqDdreIpKPKIT1y5bn9ToNcL7rUycIwJ woCHn3UyJhixcfHIJ2/FgwQgVqg+pmkexJvfsF/PO/kceMhb79e7cclQ//BVSa1I BbPTvzs2czRDgLi5MpdlYYXtC8erldd6RqYLt5Ia82W1rV7i7es6nbvYZBiimYIp T3gTzaZ52EEnf0jv2FVyrIEZYnEFUPH/IyI13DKZu19phvX0MtM4AxeaKqcm+ms/ 6eW3AJ3umnWlcIsnLNO5QxwrxzoBwm638PDzb9t72risCR6SmyBGFUBUPlMd1EH1 9VAZIhaTGg6fJBN7gR8AXvFD9CE0/gGlqmPmRBQy3XWraV3z/Cd7JtTnR527MPaW t40fzTdcAFV3lQFI6V3s =txw6 -----END PGP SIGNATURE----- --oLBj+sq0vYjzfsbl--