From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48073) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLMfH-000746-2G for qemu-devel@nongnu.org; Thu, 07 Jul 2016 23:41:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bLMfD-0006Ey-Fv for qemu-devel@nongnu.org; Thu, 07 Jul 2016 23:41:18 -0400 Received: from ozlabs.org ([103.22.144.67]:59359) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bLMfC-0006El-Kz for qemu-devel@nongnu.org; Thu, 07 Jul 2016 23:41:15 -0400 Date: Fri, 8 Jul 2016 13:42:59 +1000 From: David Gibson Message-ID: <20160708034259.GC14675@voom.fritz.box> References: <1467934423-5997-1-git-send-email-andrew.smirnov@gmail.com> <1467934423-5997-7-git-send-email-andrew.smirnov@gmail.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="G5yIW5EaChZ5gJdA" Content-Disposition: inline In-Reply-To: <1467934423-5997-7-git-send-email-andrew.smirnov@gmail.com> Subject: Re: [Qemu-devel] [PATCH 6/9] Convert cpu_memory_rw_debug to use MMUAccessType List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrey Smirnov Cc: qemu-devel@nongnu.org --G5yIW5EaChZ5gJdA Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Thu, Jul 07, 2016 at 04:33:40PM -0700, Andrey Smirnov wrote: > Convert cpu_memory_rw_debug() to use MMUAccessType as a way of > specifying memory reads/writes. This makes caller code be more obvious > in what it does (previously one had to interpret 0 or 1 and remember the > semantics of the last boolean argument of the function) and uses the > same approach used by tlb_* functions. >=20 > Signed-off-by: Andrey Smirnov My only concern here is that the constants are named *MMU*_DATA_... whereas these are physical memory accesses not involving the MMU. I can't actually see any current users of MMUAccessType which makes me a bit confused as to what it's intended meaning was. > --- > cpus.c | 2 +- > disas.c | 4 ++-- > exec.c | 14 ++++++++++---- > gdbstub.c | 3 ++- > hw/i386/kvmvapic.c | 20 +++++++++++--------- > include/exec/cpu-all.h | 2 +- > include/exec/softmmu-semi.h | 16 ++++++++-------- > monitor.c | 3 ++- > target-arm/arm-semi.c | 2 +- > target-arm/kvm64.c | 12 ++++++++---- > target-i386/helper.c | 7 ++++--- > target-i386/kvm.c | 9 +++++---- > target-ppc/kvm.c | 9 +++++---- > target-s390x/kvm.c | 9 +++++---- > target-sparc/mmu_helper.c | 8 ++++++-- > target-xtensa/xtensa-semi.c | 10 +++++----- > 16 files changed, 76 insertions(+), 54 deletions(-) >=20 > diff --git a/cpus.c b/cpus.c > index 84c3520..7aa984b 100644 > --- a/cpus.c > +++ b/cpus.c > @@ -1691,7 +1691,7 @@ void qmp_memsave(int64_t addr, int64_t size, const = char *filename, > l =3D sizeof(buf); > if (l > size) > l =3D size; > - if (cpu_memory_rw_debug(cpu, addr, buf, l, 0) !=3D 0) { > + if (cpu_memory_rw_debug(cpu, addr, buf, l, MMU_DATA_LOAD) !=3D 0= ) { > error_setg(errp, "Invalid addr 0x%016" PRIx64 "/size %" PRId= 64 > " specified", orig_addr, orig_size); > goto exit; > diff --git a/disas.c b/disas.c > index 05a7a12..75cae10 100644 > --- a/disas.c > +++ b/disas.c > @@ -39,7 +39,7 @@ target_read_memory (bfd_vma memaddr, > { > CPUDebug *s =3D container_of(info, CPUDebug, info); > =20 > - cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0); > + cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, MMU_DATA_LOAD); > return 0; > } > =20 > @@ -358,7 +358,7 @@ monitor_read_memory (bfd_vma memaddr, bfd_byte *myadd= r, int length, > if (monitor_disas_is_physical) { > cpu_physical_memory_read(memaddr, myaddr, length); > } else { > - cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, 0); > + cpu_memory_rw_debug(s->cpu, memaddr, myaddr, length, MMU_DATA_LO= AD); > } > return 0; > } > diff --git a/exec.c b/exec.c > index 5cef9fe..36a66e6 100644 > --- a/exec.c > +++ b/exec.c > @@ -2436,13 +2436,16 @@ MemoryRegion *get_system_io(void) > /* physical memory access (slow version, mainly for debug) */ > #if defined(CONFIG_USER_ONLY) > int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, > - void *b, int len, int is_write) > + void *b, int len, MMUAccessType access_type) > { > int l, flags; > target_ulong page; > void * p; > uint8_t *buf =3D b; > =20 > + g_assert(access_type =3D=3D MMU_DATA_STORE || > + access_type =3D=3D MMU_DATA_LOAD); > + > while (len > 0) { > page =3D addr & TARGET_PAGE_MASK; > l =3D (page + TARGET_PAGE_SIZE) - addr; > @@ -2451,7 +2454,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong= addr, > flags =3D page_get_flags(page); > if (!(flags & PAGE_VALID)) > return -1; > - if (is_write) { > + if (access_type =3D=3D MMU_DATA_STORE) { > if (!(flags & PAGE_WRITE)) > return -1; > /* XXX: this code should not depend on lock_user */ > @@ -3610,13 +3613,16 @@ void stq_be_phys(AddressSpace *as, hwaddr addr, u= int64_t val) > =20 > /* virtual memory access for debug (includes writing to ROM) */ > int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, > - void *b, int len, int is_write) > + void *b, int len, MMUAccessType access_type) > { > int l; > hwaddr phys_addr; > target_ulong page; > uint8_t *buf =3D b; > =20 > + g_assert(access_type =3D=3D MMU_DATA_STORE || > + access_type =3D=3D MMU_DATA_LOAD); > + > while (len > 0) { > int asidx; > MemTxAttrs attrs; > @@ -3631,7 +3637,7 @@ int cpu_memory_rw_debug(CPUState *cpu, target_ulong= addr, > if (l > len) > l =3D len; > phys_addr +=3D (addr & ~TARGET_PAGE_MASK); > - if (is_write) { > + if (access_type =3D=3D MMU_DATA_STORE) { > cpu_physical_memory_write_rom(cpu->cpu_ases[asidx].as, > phys_addr, buf, l); > } else { > diff --git a/gdbstub.c b/gdbstub.c > index 5da66f1..89cb538 100644 > --- a/gdbstub.c > +++ b/gdbstub.c > @@ -51,7 +51,8 @@ static inline int target_memory_rw_debug(CPUState *cpu,= target_ulong addr, > if (cc->memory_rw_debug) { > return cc->memory_rw_debug(cpu, addr, buf, len, is_write); > } > - return cpu_memory_rw_debug(cpu, addr, buf, len, is_write); > + return cpu_memory_rw_debug(cpu, addr, buf, len, > + is_write ? MMU_DATA_STORE : MMU_DATA_LOAD= ); > } > =20 > enum { > diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c > index c684675..68f87c8 100644 > --- a/hw/i386/kvmvapic.c > +++ b/hw/i386/kvmvapic.c > @@ -233,7 +233,7 @@ static int evaluate_tpr_instruction(VAPICROMState *s,= X86CPU *cpu, > continue; > } > if (cpu_memory_rw_debug(cs, ip - instr->length, opcode, > - sizeof(opcode), 0) < 0) { > + sizeof(opcode), MMU_DATA_LOAD) < 0) { > return -1; > } > if (opcode_matches(opcode, instr)) { > @@ -243,7 +243,8 @@ static int evaluate_tpr_instruction(VAPICROMState *s,= X86CPU *cpu, > } > return -1; > } else { > - if (cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0) < 0) { > + if (cpu_memory_rw_debug(cs, ip, opcode, > + sizeof(opcode), MMU_DATA_LOAD) < 0) { > return -1; > } > for (i =3D 0; i < ARRAY_SIZE(tpr_instr); i++) { > @@ -262,7 +263,7 @@ instruction_ok: > */ > if (cpu_memory_rw_debug(cs, ip + instr->addr_offset, > &real_tpr_addr, > - sizeof(real_tpr_addr), 0) < 0) { > + sizeof(real_tpr_addr), MMU_DATA_LOAD) < 0) { > return -1; > } > real_tpr_addr =3D le32_to_cpu(real_tpr_addr); > @@ -349,7 +350,7 @@ static int get_kpcr_number(X86CPU *cpu) > } QEMU_PACKED kpcr; > =20 > if (cpu_memory_rw_debug(CPU(cpu), env->segs[R_FS].base, > - &kpcr, sizeof(kpcr), 0) < 0 || > + &kpcr, sizeof(kpcr), MMU_DATA_LOAD) < 0 || > kpcr.self !=3D env->segs[R_FS].base) { > return -1; > } > @@ -378,7 +379,7 @@ static int vapic_enable(VAPICROMState *s, X86CPU *cpu) > =20 > static void patch_byte(X86CPU *cpu, target_ulong addr, uint8_t byte) > { > - cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, 1); > + cpu_memory_rw_debug(CPU(cpu), addr, &byte, 1, MMU_DATA_STORE); > } > =20 > static void patch_call(VAPICROMState *s, X86CPU *cpu, target_ulong ip, > @@ -388,7 +389,8 @@ static void patch_call(VAPICROMState *s, X86CPU *cpu,= target_ulong ip, > =20 > offset =3D cpu_to_le32(target - ip - 5); > patch_byte(cpu, ip, 0xe8); /* call near */ > - cpu_memory_rw_debug(CPU(cpu), ip + 1, &offset, sizeof(offset), 1); > + cpu_memory_rw_debug(CPU(cpu), ip + 1, &offset, > + sizeof(offset), MMU_DATA_STORE); > } > =20 > static void patch_instruction(VAPICROMState *s, X86CPU *cpu, target_ulon= g ip) > @@ -415,7 +417,7 @@ static void patch_instruction(VAPICROMState *s, X86CP= U *cpu, target_ulong ip) > =20 > pause_all_vcpus(); > =20 > - cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), 0); > + cpu_memory_rw_debug(cs, ip, opcode, sizeof(opcode), MMU_DATA_LOAD); > =20 > switch (opcode[0]) { > case 0x89: /* mov r32 to r/m32 */ > @@ -434,8 +436,8 @@ static void patch_instruction(VAPICROMState *s, X86CP= U *cpu, target_ulong ip) > break; > case 0xc7: /* mov imm32, r/m32 (c7/0) */ > patch_byte(cpu, ip, 0x68); /* push imm32 */ > - cpu_memory_rw_debug(cs, ip + 6, &imm32, sizeof(imm32), 0); > - cpu_memory_rw_debug(cs, ip + 1, &imm32, sizeof(imm32), 1); > + cpu_memory_rw_debug(cs, ip + 6, &imm32, sizeof(imm32), MMU_DATA_= LOAD); > + cpu_memory_rw_debug(cs, ip + 1, &imm32, sizeof(imm32), MMU_DATA_= STORE); > patch_call(s, cpu, ip + 5, handlers->set_tpr); > break; > case 0xff: /* push r/m32 */ > diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h > index 2b2f38a..062cc52 100644 > --- a/include/exec/cpu-all.h > +++ b/include/exec/cpu-all.h > @@ -302,6 +302,6 @@ void dump_opcount_info(FILE *f, fprintf_function cpu_= fprintf); > #endif /* !CONFIG_USER_ONLY */ > =20 > int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, > - void *buf, int len, int is_write); > + void *buf, int len, MMUAccessType access_type); > =20 > #endif /* CPU_ALL_H */ > diff --git a/include/exec/softmmu-semi.h b/include/exec/softmmu-semi.h > index 98e5b5c..65d933e 100644 > --- a/include/exec/softmmu-semi.h > +++ b/include/exec/softmmu-semi.h > @@ -13,7 +13,7 @@ static inline uint64_t softmmu_tget64(CPUArchState *env= , target_ulong addr) > { > uint64_t val; > =20 > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 0); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, MMU_DATA_LOAD); > return tswap64(val); > } > =20 > @@ -21,7 +21,7 @@ static inline uint32_t softmmu_tget32(CPUArchState *env= , target_ulong addr) > { > uint32_t val; > =20 > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 0); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, MMU_DATA_LOAD); > return tswap32(val); > } > =20 > @@ -29,7 +29,7 @@ static inline uint32_t softmmu_tget8(CPUArchState *env,= target_ulong addr) > { > uint8_t val; > =20 > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, 0); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 1, MMU_DATA_LOAD); > return val; > } > =20 > @@ -42,14 +42,14 @@ static inline void softmmu_tput64(CPUArchState *env, > target_ulong addr, uint64_t val) > { > val =3D tswap64(val); > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, 1); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 8, MMU_DATA_STORE); > } > =20 > static inline void softmmu_tput32(CPUArchState *env, > target_ulong addr, uint32_t val) > { > val =3D tswap32(val); > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, 1); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &val, 4, MMU_DATA_STORE); > } > #define put_user_u64(arg, p) ({ softmmu_tput64(env, p, arg) ; 0; }) > #define put_user_u32(arg, p) ({ softmmu_tput32(env, p, arg) ; 0; }) > @@ -62,7 +62,7 @@ static void *softmmu_lock_user(CPUArchState *env, > /* TODO: Make this something that isn't fixed size. */ > p =3D malloc(len); > if (p && copy) { > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 0); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, MMU_DATA_LOA= D); > } > return p; > } > @@ -78,7 +78,7 @@ static char *softmmu_lock_user_string(CPUArchState *env= , target_ulong addr) > return NULL; > } > do { > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, 0); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, &c, 1, MMU_DATA_LOAD= ); > addr++; > *(p++) =3D c; > } while (c); > @@ -89,7 +89,7 @@ static void softmmu_unlock_user(CPUArchState *env, void= *p, target_ulong addr, > target_ulong len) > { > if (len) { > - cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, 1); > + cpu_memory_rw_debug(ENV_GET_CPU(env), addr, p, len, MMU_DATA_STO= RE); > } > free(p); > } > diff --git a/monitor.c b/monitor.c > index a27e115..e622d9b 100644 > --- a/monitor.c > +++ b/monitor.c > @@ -1268,7 +1268,8 @@ static void memory_dump(Monitor *mon, int count, in= t format, int wsize, > if (is_physical) { > cpu_physical_memory_read(addr, buf, l); > } else { > - if (cpu_memory_rw_debug(mon_get_cpu(), addr, buf, l, 0) < 0)= { > + if (cpu_memory_rw_debug(mon_get_cpu(), addr, buf, > + l, MMU_DATA_LOAD) < 0) { > monitor_printf(mon, " Cannot access memory\n"); > break; > } > diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c > index 03c959d..42a2856 100644 > --- a/target-arm/arm-semi.c > +++ b/target-arm/arm-semi.c > @@ -187,7 +187,7 @@ static void arm_semi_flen_cb(CPUState *cs, target_ulo= ng ret, target_ulong err) > /* The size is always stored in big-endian order, extract > the value. We assume the size always fit in 32 bits. */ > uint32_t size; > - cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, &size, 4, 0); > + cpu_memory_rw_debug(cs, arm_flen_buf(cpu) + 32, &size, 4, MMU_DATA_L= OAD); > size =3D be32_to_cpu(size); > if (is_a64(env)) { > env->xregs[0] =3D size; > diff --git a/target-arm/kvm64.c b/target-arm/kvm64.c > index 7ba5acd..ed324fd 100644 > --- a/target-arm/kvm64.c > +++ b/target-arm/kvm64.c > @@ -874,8 +874,10 @@ static const uint32_t brk_insn =3D 0xd4200000; > int kvm_arch_insert_sw_breakpoint(CPUState *cs, struct kvm_sw_breakpoint= *bp) > { > if (have_guest_debug) { > - if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 0) || > - cpu_memory_rw_debug(cs, bp->pc, &brk_insn, 4, 1)) { > + if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > + 4, MMU_DATA_LOAD) || > + cpu_memory_rw_debug(cs, bp->pc, &brk_insn, > + 4, MMU_DATA_STORE)) { > return -EINVAL; > } > return 0; > @@ -890,9 +892,11 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, stru= ct kvm_sw_breakpoint *bp) > static uint32_t brk; > =20 > if (have_guest_debug) { > - if (cpu_memory_rw_debug(cs, bp->pc, &brk, 4, 0) || > + if (cpu_memory_rw_debug(cs, bp->pc, &brk, > + 4, MMU_DATA_LOAD) || > brk !=3D brk_insn || > - cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 4, 1)) { > + cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > + 4, MMU_DATA_STORE)) { > return -EINVAL; > } > return 0; > diff --git a/target-i386/helper.c b/target-i386/helper.c > index 6b10a8e..7f176fa 100644 > --- a/target-i386/helper.c > +++ b/target-i386/helper.c > @@ -555,7 +555,8 @@ void x86_cpu_dump_state(CPUState *cs, FILE *f, fprint= f_function cpu_fprintf, > =20 > cpu_fprintf(f, "Code=3D"); > for (i =3D 0; i < DUMP_CODE_BYTES_TOTAL; i++) { > - if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) = =3D=3D 0) { > + if (cpu_memory_rw_debug(cs, base - offs + i, &code, > + 1, MMU_DATA_LOAD) =3D=3D 0) { > snprintf(codestr, sizeof(codestr), "%02x", code); > } else { > snprintf(codestr, sizeof(codestr), "??"); > @@ -1286,8 +1287,8 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsig= ned int selector, > index =3D selector & ~7; > ptr =3D dt->base + index; > if ((index + 7) > dt->limit > - || cpu_memory_rw_debug(cs, ptr, &e1, sizeof(e1), 0) !=3D 0 > - || cpu_memory_rw_debug(cs, ptr+4, &e2, sizeof(e2), 0) !=3D 0) > + || cpu_memory_rw_debug(cs, ptr, &e1, sizeof(e1), MMU_DATA_LOAD) = !=3D 0 > + || cpu_memory_rw_debug(cs, ptr+4, &e2, sizeof(e2), MMU_DATA_LOAD= ) !=3D 0) > return 0; > =20 > *base =3D ((e1 >> 16) | ((e2 & 0xff) << 16) | (e2 & 0xff000000)); > diff --git a/target-i386/kvm.c b/target-i386/kvm.c > index dc0cf6b..beefcf4 100644 > --- a/target-i386/kvm.c > +++ b/target-i386/kvm.c > @@ -2866,8 +2866,8 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, str= uct kvm_sw_breakpoint *bp) > { > uint8_t int3 =3D 0xcc; > =20 > - if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 0) || > - cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 1)) { > + if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, MMU_DATA_LOA= D) || > + cpu_memory_rw_debug(cs, bp->pc, &int3, 1, MMU_DATA_STORE)) { > return -EINVAL; > } > return 0; > @@ -2877,8 +2877,9 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, str= uct kvm_sw_breakpoint *bp) > { > uint8_t int3; > =20 > - if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, 0) || int3 !=3D 0xcc || > - cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, 1)) { > + if (cpu_memory_rw_debug(cs, bp->pc, &int3, 1, MMU_DATA_LOAD) || > + int3 !=3D 0xcc || > + cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, 1, MMU_DATA_STO= RE)) { > return -EINVAL; > } > return 0; > diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c > index efa257b..0a6032a 100644 > --- a/target-ppc/kvm.c > +++ b/target-ppc/kvm.c > @@ -1433,8 +1433,8 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, str= uct kvm_sw_breakpoint *bp) > uint32_t sc =3D debug_inst_opcode; > =20 > if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > - sizeof(sc), 0) || > - cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 1)) { > + sizeof(sc), MMU_DATA_LOAD) || > + cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), MMU_DATA_STORE)= ) { > return -EINVAL; > } > =20 > @@ -1445,10 +1445,11 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, s= truct kvm_sw_breakpoint *bp) > { > uint32_t sc; > =20 > - if (cpu_memory_rw_debug(cs, bp->pc, &sc, sizeof(sc), 0) || > + if (cpu_memory_rw_debug(cs, bp->pc, &sc, > + sizeof(sc), MMU_DATA_LOAD) || > sc !=3D debug_inst_opcode || > cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > - sizeof(sc), 1)) { > + sizeof(sc), MMU_DATA_STORE)) { > return -EINVAL; > } > =20 > diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c > index fb7dd55..c55d853 100644 > --- a/target-s390x/kvm.c > +++ b/target-s390x/kvm.c > @@ -672,9 +672,9 @@ int kvm_arch_insert_sw_breakpoint(CPUState *cs, struc= t kvm_sw_breakpoint *bp) > { > =20 > if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > - sizeof(diag_501), 0) || > + sizeof(diag_501), MMU_DATA_LOAD) || > cpu_memory_rw_debug(cs, bp->pc, diag_501, > - sizeof(diag_501), 1)) { > + sizeof(diag_501), MMU_DATA_STORE)) { > return -EINVAL; > } > return 0; > @@ -684,12 +684,13 @@ int kvm_arch_remove_sw_breakpoint(CPUState *cs, str= uct kvm_sw_breakpoint *bp) > { > uint8_t t[sizeof(diag_501)]; > =20 > - if (cpu_memory_rw_debug(cs, bp->pc, t, sizeof(diag_501), 0)) { > + if (cpu_memory_rw_debug(cs, bp->pc, t, > + sizeof(diag_501), MMU_DATA_LOAD)) { > return -EINVAL; > } else if (memcmp(t, diag_501, sizeof(diag_501))) { > return -EINVAL; > } else if (cpu_memory_rw_debug(cs, bp->pc, &bp->saved_insn, > - sizeof(diag_501), 1)) { > + sizeof(diag_501), MMU_DATA_STORE)) { > return -EINVAL; > } > =20 > diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c > index 32b629f..1cf7c99 100644 > --- a/target-sparc/mmu_helper.c > +++ b/target-sparc/mmu_helper.c > @@ -398,7 +398,10 @@ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr ad= dress, > /* Handle access before this window. */ > if (addr < fp) { > len1 =3D fp - addr; > - if (cpu_memory_rw_debug(cs, addr, buf, len1, is_write) != =3D 0) { > + if (cpu_memory_rw_debug(cs, addr, buf, len1, > + is_write ? > + MMU_DATA_STORE : > + MMU_DATA_LOAD) !=3D 0) { > return -1; > } > addr +=3D len1; > @@ -434,7 +437,8 @@ int sparc_cpu_memory_rw_debug(CPUState *cs, vaddr add= ress, > } > } > } > - return cpu_memory_rw_debug(cs, addr, buf, len, is_write); > + return cpu_memory_rw_debug(cs, addr, buf, len, > + is_write ? MMU_DATA_STORE : MMU_DATA_LOAD= ); > } > =20 > #else /* !TARGET_SPARC64 */ > diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c > index ec199ac..161a5e0 100644 > --- a/target-xtensa/xtensa-semi.c > +++ b/target-xtensa/xtensa-semi.c > @@ -202,7 +202,7 @@ void HELPER(simcall)(CPUXtensaState *env) > =20 > for (i =3D 0; i < ARRAY_SIZE(name); ++i) { > rc =3D cpu_memory_rw_debug(cs, regs[3] + i, > - &name[i], 1, 0); > + &name[i], 1, MMU_DATA_LOAD); > if (rc !=3D 0 || name[i] =3D=3D 0) { > break; > } > @@ -246,8 +246,8 @@ void HELPER(simcall)(CPUXtensaState *env) > FD_SET(fd, &fdset); > =20 > if (target_tv) { > - cpu_memory_rw_debug(cs, target_tv, > - target_tvv, sizeof(target_tvv), 0); > + cpu_memory_rw_debug(cs, target_tv, target_tvv, > + sizeof(target_tvv), MMU_DATA_LOAD); > tv.tv_sec =3D (int32_t)tswap32(target_tvv[0]); > tv.tv_usec =3D (int32_t)tswap32(target_tvv[1]); > } > @@ -281,8 +281,8 @@ void HELPER(simcall)(CPUXtensaState *env) > }; > =20 > argv.argptr[0] =3D tswap32(regs[3] + offsetof(struct Argv, t= ext)); > - cpu_memory_rw_debug(cs, > - regs[3], &argv, sizeof(argv), 1); > + cpu_memory_rw_debug(cs, regs[3], &argv, > + sizeof(argv), MMU_DATA_STORE); > } > break; > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --G5yIW5EaChZ5gJdA Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXfyFDAAoJEGw4ysog2bOSB9cP/RT+Nu7PA5I7DGnBb0XhMNeM VnDRGDRRrKuIr63ouwGDGM9Wc6DSnPSmm63pulDS3d8etFXSCIArxEbymNA+krCY AER8deEb107SDvWhlQLc9FDo2MPLIYb8hslcoutUyDql/SyUkcez0wUMZkO2qhtH QwawcLiwtEmkvppuC+hLoMzEmnOTYe9+RRU8cHpU+7eTaGaLd5TvQi4exX9G5909 CcQRrYGJO90Y1sElbylgLfoPM1MVUvjc4MRfF84PtJENNA6P6TOI4otiD4oLGnPu 9s91e1p4+ysxOjleUQ9pKFhqXC66k/29cvSCd1t75OVuoNQf/Ny6LpgdkosbAvZj vH4OFMdMua2rkatsGD5xPER2TcePDx7QFjx4Hrh6e8o6ryor8ZF2T3rYowhvhVfX LTas2tkWhMIAkCzd1svYjpDbjYslqnYuZElxEpZKkhidK6TnxB/WvseFd/PoSdaN C1cO9miizCvOXHuzPFh5l4TcZoKn68LOU1JRcywi42RK0egWpl0swdaqeGg/vcQC bi4qzrqKx3W8Hg8+AKjnKJZm0sSoIjTYzBmL4Zg4LzopLiY+K3Iyd6YUJdbCTlkY P3ZDsHUPgxFZHZQXA9xCugY6n2hO+ost6dQGCkDGW/PqjyIay7RRLy6ogA2wgajN ADtaSB3R3w4U+QIjIN3+ =4xCA -----END PGP SIGNATURE----- --G5yIW5EaChZ5gJdA--