From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36609) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMQoF-0002z9-5i for qemu-devel@nongnu.org; Sun, 10 Jul 2016 22:19:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMQoB-0002GD-DO for qemu-devel@nongnu.org; Sun, 10 Jul 2016 22:18:57 -0400 Date: Mon, 11 Jul 2016 11:55:55 +1000 From: David Gibson Message-ID: <20160711015555.GG16355@voom.fritz.box> References: <1467355319-28406-1-git-send-email-david@gibson.dropbear.id.au> <1467355319-28406-6-git-send-email-david@gibson.dropbear.id.au> <1468032411.20552.21.camel@kernel.crashing.org> <1468032757.20552.22.camel@au1.ibm.com> <1468033216.20552.23.camel@kernel.crashing.org> <1468033695.20552.24.camel@kernel.crashing.org> <1468035691.20552.29.camel@kernel.crashing.org> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="EDJsL2R9iCFAt7IV" Content-Disposition: inline In-Reply-To: <1468035691.20552.29.camel@kernel.crashing.org> Subject: Re: [Qemu-devel] [PATCH v2] ppc: Fix support for odd MSR combinations List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Benjamin Herrenschmidt Cc: Mark Cave-Ayland , peter.maydell@linaro.org, qemu-devel@nongnu.org, qemu-ppc@nongnu.org, =?iso-8859-1?Q?C=E9dric?= Le Goater --EDJsL2R9iCFAt7IV Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Sat, Jul 09, 2016 at 01:41:31PM +1000, Benjamin Herrenschmidt wrote: > MacOS uses an architecturally illegal MSR combination that > seems nonetheless supported by 32-bit processors, which is > to have MSR[PR]=3D1 and one or more of MSR[DR/IR/EE]=3D0. >=20 > This adds support for it. To work properly we need to also > properly include support for PR=3D1,{I,D}R=3D0 to the MMU index > used by the qemu TLB. >=20 > Signed-off-by: Benjamin Herrenschmidt Applied to ppc-for-2.7, thanks. > --- >=20 > v2. Use the correct flags >=20 > target-ppc/helper_regs.h | 46 ++++++++++++++++++++++--------------------= ---- > 1 file changed, 22 insertions(+), 24 deletions(-) >=20 > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index 8fdfa5c..466ad67 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -41,17 +41,19 @@ static inline void hreg_swap_gpr_tgpr(CPUPPCState *en= v) > =20 > static inline void hreg_compute_mem_idx(CPUPPCState *env) > { > - /* This is our encoding for server processors > + /* This is our encoding for server processors. The architecture > + * specifies that there is no such thing as userspace with > + * translation off, however it appears that MacOS does it and > + * some 32-bit CPUs support it. Weird... > * > * 0 =3D Guest User space virtual mode > * 1 =3D Guest Kernel space virtual mode > - * 2 =3D Guest Kernel space real mode > - * 3 =3D HV User space virtual mode > - * 4 =3D HV Kernel space virtual mode > - * 5 =3D HV Kernel space real mode > - * > - * The combination PR=3D1 IR&DR=3D0 is invalid, we will treat > - * it as IR=3DDR=3D1 > + * 2 =3D Guest User space real mode > + * 3 =3D Guest Kernel space real mode > + * 4 =3D HV User space virtual mode > + * 5 =3D HV Kernel space virtual mode > + * 6 =3D HV User space real mode > + * 7 =3D HV Kernel space real mode > * > * For BookE, we need 8 MMU modes as follow: > * > @@ -71,20 +73,11 @@ static inline void hreg_compute_mem_idx(CPUPPCState *= env) > env->immu_idx +=3D msr_gs ? 4 : 0; > env->dmmu_idx +=3D msr_gs ? 4 : 0; > } else { > - /* First calucalte a base value independent of HV */ > - if (msr_pr !=3D 0) { > - /* User space, ignore IR and DR */ > - env->immu_idx =3D env->dmmu_idx =3D 0; > - } else { > - /* Kernel, setup a base I/D value */ > - env->immu_idx =3D msr_ir ? 1 : 2; > - env->dmmu_idx =3D msr_dr ? 1 : 2; > - } > - /* Then offset it for HV */ > - if (msr_hv) { > - env->immu_idx +=3D 3; > - env->dmmu_idx +=3D 3; > - } > + env->immu_idx =3D env->dmmu_idx =3D msr_pr ? 0 : 1; > + env->immu_idx +=3D msr_ir ? 0 : 2; > + env->dmmu_idx +=3D msr_dr ? 0 : 2; > + env->immu_idx +=3D msr_hv ? 4 : 0; > + env->dmmu_idx +=3D msr_hv ? 4 : 0; > } > } > =20 > @@ -136,8 +129,13 @@ static inline int hreg_store_msr(CPUPPCState *env, t= arget_ulong value, > /* Change the exception prefix on PowerPC 601 */ > env->excp_prefix =3D ((value >> MSR_EP) & 1) * 0xFFF00000; > } > - /* If PR=3D1 then EE, IR and DR must be 1 */ > - if ((value >> MSR_PR) & 1) { > + /* If PR=3D1 then EE, IR and DR must be 1 > + * > + * Note: We only enforce this on 64-bit processors. It appears that > + * 32-bit implementations supports PR=3D1 and EE/DR/IR=3D0 and MacOS > + * exploits it. > + */ > + if ((env->insns_flags & PPC_64B) && ((value >> MSR_PR) & 1)) { > value |=3D (1 << MSR_EE) | (1 << MSR_DR) | (1 << MSR_IR); > } > #endif >=20 >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --EDJsL2R9iCFAt7IV Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXgvyrAAoJEGw4ysog2bOSrSAQAKVQxFkJ3DL1UP/Vq6Ycah+Y fk7e3euvXE42CVZtXvbmpCRxT0duEPucqRNLEolz0SDQfxyp1/0TfiQPFgp9If4p g00NcQDQx4/JnVY4EfEGmoVMrYJZ3mbyy3TMPg8No+4Si1gYMood2Jc+o4DBznJY OqerqP1CD0aalVvL9wTTCnuMvxstPISeQbHoJeNrHkdekkLhchUOGhnQ8LRejEp8 i2KhCZBZpyTji7KIlU2HOWw/0GnMLr+MBiVZEMaI0z2yA9ubcl8Aoxyxc8hgtDHz CIueBg0LcGbRIE5qxQiJl7zou+rXf2FaFUCKzWwdjdlTPDPLitY3dBEGfFyfNJ5U elNeogF6FrXPe5KIpFJdXv1q6CdXfP2viMAkB9g00AzUW5aW4t8KNuON53GUjsNB lr7SCPbjpP3RJrFZksAzwBdUma+m7BoiJyINJ478kiMaWd92J0y2VOqPU7iQuYsy Wd3P7VNG3gQjnF5DOk7yTHqWgMwQxn85r8NYok3VQl5oURGXYg1AzwIuITtecXhh NHZlek3bPnLWtB2QzpljS2+8z2jG7QytwByWLxkSLyIeXbcD290yckXrkIzAUk3b iLb4nqpByHJjJupoNKfK3o2ycEu0+zqar6adogYFMnec8xQoln4/DAjx1Q6R2I2D A63WMDltw4VklFT/Dfx9 =bRm3 -----END PGP SIGNATURE----- --EDJsL2R9iCFAt7IV--