From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57610) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMaLe-0004BC-QY for qemu-devel@nongnu.org; Mon, 11 Jul 2016 08:30:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bMaLa-00069t-PB for qemu-devel@nongnu.org; Mon, 11 Jul 2016 08:30:06 -0400 Received: from mx1.redhat.com ([209.132.183.28]:53529) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bMaLa-00069h-H5 for qemu-devel@nongnu.org; Mon, 11 Jul 2016 08:30:02 -0400 Received: from int-mx13.intmail.prod.int.phx2.redhat.com (int-mx13.intmail.prod.int.phx2.redhat.com [10.5.11.26]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 93F4A46213 for ; Mon, 11 Jul 2016 12:30:00 +0000 (UTC) Date: Mon, 11 Jul 2016 13:29:56 +0100 From: "Dr. David Alan Gilbert" Message-ID: <20160711122956.GC3165@work-vm> References: <1467990099-27853-1-git-send-email-dgilbert@redhat.com> <1467990099-27853-6-git-send-email-dgilbert@redhat.com> <20160708231601.GR4131@thinpad.lan.raisama.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20160708231601.GR4131@thinpad.lan.raisama.net> Subject: Re: [Qemu-devel] [PATCH v4 5/5] x86: Set physical address bits based on host List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Eduardo Habkost Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, marcel@redhat.com, mst@redhat.com, kraxel@redhat.com * Eduardo Habkost (ehabkost@redhat.com) wrote: > On Fri, Jul 08, 2016 at 04:01:39PM +0100, Dr. David Alan Gilbert (git) wrote: > > From: "Dr. David Alan Gilbert" > > > > Add the host-phys-bits boolean property, if true, take phys-bits > > from the hosts physical bits value, overriding either the default > > or the user specified value. > > > > We can also use the value we read from the host to check the users > > explicitly set value and warn them if it doesn't match. > > > > Signed-off-by: Dr. David Alan Gilbert > > --- > [...] > > @@ -2952,28 +2977,57 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) > > & CPUID_EXT2_AMD_ALIASES); > > } > > > > + /* For 64bit systems think about the number of physical bits to present. > > + * ideally this should be the same as the host; anything other than matching > > + * the host can cause incorrect guest behaviour. > > + * QEMU used to pick the magic value of 40 bits that corresponds to > > + * consumer AMD devices but nothing else. > > + */ > > + if (cpu->host_phys_bits && !kvm_enabled()) { > > + error_setg(errp, "phys-bits can not be read from the host in" > > + " TCG mode"); > > + return; > > + } > > + > > if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) { > > - /* 0 is a special meaning 'use the old default', which matches > > - * the value used by TCG (40). > > - */ > > - if (cpu->phys_bits == 0) { > > - cpu->phys_bits = TCG_PHYS_ADDR_BITS; > > - } > > if (kvm_enabled()) { > > - if (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || > > - cpu->phys_bits < 32) { > > + uint32_t host_phys_bits = x86_host_phys_bits(); > > + static bool warned; > > + > > + if (cpu->host_phys_bits) { > > + /* The user asked for us to use the host physical bits */ > > + cpu->phys_bits = host_phys_bits; > > + } > > + > > + /* Print a warning if the user set it to a value that's not the > > + * host value. > > + */ > > + if (cpu->phys_bits != host_phys_bits && cpu->phys_bits != 0 && > > + !warned) { > > + error_report("Warning: Host physical bits (%u)" > > + " does not match phys-bits property (%u)", > > + host_phys_bits, cpu->phys_bits); > > + warned = true; > > + } > > + > > + if (cpu->phys_bits && > > + (cpu->phys_bits > TARGET_PHYS_ADDR_SPACE_BITS || > > + cpu->phys_bits < 32)) { > > error_setg(errp, "phys-bits should be between 32 and %u " > > " (but is %u)", > > TARGET_PHYS_ADDR_SPACE_BITS, cpu->phys_bits); > > return; > > } > > } else { > > - if (cpu->phys_bits != TCG_PHYS_ADDR_BITS) { > > + if (cpu->phys_bits && cpu->phys_bits != TCG_PHYS_ADDR_BITS) { > > error_setg(errp, "TCG only supports phys-bits=%u", > > TCG_PHYS_ADDR_BITS); > > return; > > } > > } > > + if (cpu->phys_bits == 0 && !cpu->host_phys_bits) { > > Why the !cpu->host_phys_bits check? It seems to be impossible to > have (cpu->host_phys_bits == true && cpu->phys_bits == 0) here. Right; I think I added that before I added the TCG check at the top. > > + cpu->phys_bits = TCG_PHYS_ADDR_BITS; > > + } > > } else { > > /* For 32 bit systems don't use the user set value, but keep > > * phys_bits consistent with what we tell the guest. > > Shouldn't we return error if host-phys-bits is set in 32-bit > mode? Yes; easy to add. Do you want me to repost just this patch or the whole set? Dave > > @@ -3290,6 +3344,7 @@ static Property x86_cpu_properties[] = { > > DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false), > > DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true), > > DEFINE_PROP_UINT32("phys-bits", X86CPU, phys_bits, 0), > > + DEFINE_PROP_BOOL("host-phys-bits", X86CPU, host_phys_bits, false), > > DEFINE_PROP_BOOL("fill-mtrr-mask", X86CPU, fill_mtrr_mask, true), > > DEFINE_PROP_UINT32("level", X86CPU, env.cpuid_level, 0), > > DEFINE_PROP_UINT32("xlevel", X86CPU, env.cpuid_xlevel, 0), > > diff --git a/target-i386/cpu.h b/target-i386/cpu.h > > index 9d79146..3c4e64a 100644 > > --- a/target-i386/cpu.h > > +++ b/target-i386/cpu.h > > @@ -1184,6 +1184,9 @@ struct X86CPU { > > /* if true fill the top bits of the MTRR_PHYSMASKn variable range */ > > bool fill_mtrr_mask; > > > > + /* if true override the phys_bits value with a value read from the host */ > > + bool host_phys_bits; > > + > > /* Number of physical address bits supported */ > > uint32_t phys_bits; > > > > -- > > 2.7.4 > > > > -- > Eduardo -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK