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From: David Gibson <david@gibson.dropbear.id.au>
To: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
	bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com,
	benh@kernel.crashing.org,
	Vivek Andrew Sha <vivekandrewsha@gmail.com>
Subject: Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
Date: Wed, 27 Jul 2016 16:05:22 +1000	[thread overview]
Message-ID: <20160727060522.GK17429@voom.fritz.box> (raw)
In-Reply-To: <1469561218-3067-6-git-send-email-nikunj@linux.vnet.ibm.com>

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On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> 
> Adds Vector Shift Right Variable instruction.
> 
> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h     |  1 +
>  target-ppc/int_helper.c | 17 +++++++++++++++++
>  target-ppc/translate.c  |  2 ++
>  3 files changed, 20 insertions(+)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9703f85..8eada2f 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
>  DEF_HELPER_3(vsld, void, avr, avr, avr)
>  DEF_HELPER_3(vslo, void, avr, avr, avr)
>  DEF_HELPER_3(vsro, void, avr, avr, avr)
> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
>  DEF_HELPER_3(vslv, void, avr, avr, avr)
>  DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
>  DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 412398f..f4776f0 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>      }
>  }
>  
> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> +    int i;
> +    unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
> +
> +    src[0] = 0;
> +    for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> +        src[i + 1] = a->u8[i];
> +    }
> +
> +    for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> +        shift = b->u8[i] & 0x7;               /* extract shift value */
> +        bytes = (src[i] << 8) + src[i + 1];     /* extract adjacent bytes */

I think you should be able to construct bytes on the fly without
pre-generating teh whole of src, as you already did for vslv.

> +        r->u8[i] = (bytes >> shift) & 0xFF;   /* shift and store result */
> +    }
> +}
> +
>  void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
>  {
>      int sh = shift & 0xf;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 473f21a..3382cd0 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
>  GEN_VXFORM(vsrad, 2, 15);
>  GEN_VXFORM(vslo, 6, 16);
>  GEN_VXFORM(vsro, 6, 17);
> +GEN_VXFORM(vsrv, 2, 28);
>  GEN_VXFORM(vslv, 2, 29);
>  GEN_VXFORM(vaddcuw, 0, 6);
>  GEN_VXFORM(vsubcuw, 0, 22);
> @@ -10943,6 +10944,7 @@ GEN_VXFORM(vsraw, 2, 14),
>  GEN_VXFORM_207(vsrad, 2, 15),
>  GEN_VXFORM(vslo, 6, 16),
>  GEN_VXFORM(vsro, 6, 17),
> +GEN_VXFORM(vsrv, 2, 28),
>  GEN_VXFORM(vslv, 2, 29),
>  GEN_VXFORM(vaddcuw, 0, 6),
>  GEN_VXFORM(vsubcuw, 0, 22),

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2016-07-27  6:07 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions Nikunj A Dadhania
2016-07-27  5:42   ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
2016-07-27  5:52   ` David Gibson
2016-07-27  6:19     ` Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
2016-07-27  5:57   ` David Gibson
2016-07-27  6:22     ` Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction Nikunj A Dadhania
2016-07-27  6:03   ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction Nikunj A Dadhania
2016-07-27  6:05   ` David Gibson [this message]
2016-07-27  6:31     ` Nikunj A Dadhania
2016-07-27  6:48       ` David Gibson
2016-07-27  6:57         ` Nikunj A Dadhania
2016-07-27  7:02           ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
2016-07-27  6:07   ` David Gibson
2016-07-28  4:33 ` [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 David Gibson
2016-07-28  6:06   ` Nikunj A Dadhania

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