* [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 5:42 ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
` (5 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh, Sandipan Das
From: Sandipan Das <sandipandas1990@gmail.com>
DFP Test Significance Immediate [Quad]
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/dfp_helper.c | 35 +++++++++++++++++++++++++++++++++++
target-ppc/helper.h | 2 ++
target-ppc/translate.c | 22 ++++++++++++++++++++++
3 files changed, 59 insertions(+)
diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
index db0ede6..9164fe7 100644
--- a/target-ppc/dfp_helper.c
+++ b/target-ppc/dfp_helper.c
@@ -647,6 +647,41 @@ uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b) \
DFP_HELPER_TSTSF(dtstsf, 64)
DFP_HELPER_TSTSF(dtstsfq, 128)
+#define DFP_HELPER_TSTSFI(op, size) \
+uint32_t helper_##op(CPUPPCState *env, uint32_t a, uint64_t *b) \
+{ \
+ struct PPC_DFP dfp; \
+ unsigned uim; \
+ \
+ dfp_prepare_decimal##size(&dfp, 0, b, env); \
+ \
+ uim = a & 0x3F; \
+ \
+ if (unlikely(decNumberIsSpecial(&dfp.b))) { \
+ dfp.crbf = 1; \
+ } else if (uim == 0) { \
+ dfp.crbf = 4; \
+ } else if (unlikely(decNumberIsZero(&dfp.b))) { \
+ /* Zero has no sig digits */ \
+ dfp.crbf = 4; \
+ } else { \
+ unsigned nsd = dfp.b.digits; \
+ if (uim < nsd) { \
+ dfp.crbf = 8; \
+ } else if (uim > nsd) { \
+ dfp.crbf = 4; \
+ } else { \
+ dfp.crbf = 2; \
+ } \
+ } \
+ \
+ dfp_set_FPCC_from_CRBF(&dfp); \
+ return dfp.crbf; \
+}
+
+DFP_HELPER_TSTSFI(dtstsfi, 64)
+DFP_HELPER_TSTSFI(dtstsfiq, 128)
+
static void QUA_PPs(struct PPC_DFP *dfp)
{
dfp_set_FPRF_from_FRT(dfp);
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9e4bb7b..68fd19e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -645,6 +645,8 @@ DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp)
+DEF_HELPER_3(dtstsfi, i32, env, i32, fprp)
+DEF_HELPER_3(dtstsfiq, i32, env, i32, fprp)
DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index d522566..23ef538 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -8678,6 +8678,24 @@ static void gen_##name(DisasContext *ctx) \
tcg_temp_free_ptr(rb); \
}
+#define GEN_DFP_BF_I_B(name) \
+static void gen_##name(DisasContext *ctx) \
+{ \
+ TCGv_i32 uim; \
+ TCGv_ptr rb; \
+ if (unlikely(!ctx->fpu_enabled)) { \
+ gen_exception(ctx, POWERPC_EXCP_FPU); \
+ return; \
+ } \
+ gen_update_nip(ctx, ctx->nip - 4); \
+ uim = tcg_const_i32(UIMM5(ctx->opcode)); \
+ rb = gen_fprp_ptr(rB(ctx->opcode)); \
+ gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
+ cpu_env, uim, rb); \
+ tcg_temp_free_i32(uim); \
+ tcg_temp_free_ptr(rb); \
+}
+
#define GEN_DFP_BF_A_DCM(name) \
static void gen_##name(DisasContext *ctx) \
{ \
@@ -8805,6 +8823,8 @@ GEN_DFP_BF_A_B(dtstex)
GEN_DFP_BF_A_B(dtstexq)
GEN_DFP_BF_A_B(dtstsf)
GEN_DFP_BF_A_B(dtstsfq)
+GEN_DFP_BF_I_B(dtstsfi)
+GEN_DFP_BF_I_B(dtstsfiq)
GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
@@ -11456,6 +11476,8 @@ GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
+GEN_DFP_BF_A_B(dtstsfi, 0x03, 0x15),
+GEN_DFP_BF_A_Bp(dtstsfiq, 0x03, 0x15),
GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions Nikunj A Dadhania
@ 2016-07-27 5:42 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2016-07-27 5:42 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Sandipan Das
[-- Attachment #1: Type: text/plain, Size: 6344 bytes --]
On Wed, Jul 27, 2016 at 12:56:53AM +0530, Nikunj A Dadhania wrote:
> From: Sandipan Das <sandipandas1990@gmail.com>
>
> DFP Test Significance Immediate [Quad]
>
> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/dfp_helper.c | 35 +++++++++++++++++++++++++++++++++++
> target-ppc/helper.h | 2 ++
> target-ppc/translate.c | 22 ++++++++++++++++++++++
> 3 files changed, 59 insertions(+)
>
> diff --git a/target-ppc/dfp_helper.c b/target-ppc/dfp_helper.c
> index db0ede6..9164fe7 100644
> --- a/target-ppc/dfp_helper.c
> +++ b/target-ppc/dfp_helper.c
> @@ -647,6 +647,41 @@ uint32_t helper_##op(CPUPPCState *env, uint64_t *a, uint64_t *b) \
> DFP_HELPER_TSTSF(dtstsf, 64)
> DFP_HELPER_TSTSF(dtstsfq, 128)
>
> +#define DFP_HELPER_TSTSFI(op, size) \
> +uint32_t helper_##op(CPUPPCState *env, uint32_t a, uint64_t *b) \
> +{ \
> + struct PPC_DFP dfp; \
> + unsigned uim; \
> + \
> + dfp_prepare_decimal##size(&dfp, 0, b, env); \
> + \
> + uim = a & 0x3F; \
> + \
> + if (unlikely(decNumberIsSpecial(&dfp.b))) { \
> + dfp.crbf = 1; \
> + } else if (uim == 0) { \
> + dfp.crbf = 4; \
> + } else if (unlikely(decNumberIsZero(&dfp.b))) { \
> + /* Zero has no sig digits */ \
> + dfp.crbf = 4; \
> + } else { \
> + unsigned nsd = dfp.b.digits; \
> + if (uim < nsd) { \
> + dfp.crbf = 8; \
> + } else if (uim > nsd) { \
> + dfp.crbf = 4; \
> + } else { \
> + dfp.crbf = 2; \
> + } \
> + } \
> + \
> + dfp_set_FPCC_from_CRBF(&dfp); \
> + return dfp.crbf; \
> +}
> +
> +DFP_HELPER_TSTSFI(dtstsfi, 64)
> +DFP_HELPER_TSTSFI(dtstsfiq, 128)
> +
> static void QUA_PPs(struct PPC_DFP *dfp)
> {
> dfp_set_FPRF_from_FRT(dfp);
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9e4bb7b..68fd19e 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -645,6 +645,8 @@ DEF_HELPER_3(dtstex, i32, env, fprp, fprp)
> DEF_HELPER_3(dtstexq, i32, env, fprp, fprp)
> DEF_HELPER_3(dtstsf, i32, env, fprp, fprp)
> DEF_HELPER_3(dtstsfq, i32, env, fprp, fprp)
> +DEF_HELPER_3(dtstsfi, i32, env, i32, fprp)
> +DEF_HELPER_3(dtstsfiq, i32, env, i32, fprp)
> DEF_HELPER_5(dquai, void, env, fprp, fprp, i32, i32)
> DEF_HELPER_5(dquaiq, void, env, fprp, fprp, i32, i32)
> DEF_HELPER_5(dqua, void, env, fprp, fprp, fprp, i32)
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index d522566..23ef538 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -8678,6 +8678,24 @@ static void gen_##name(DisasContext *ctx) \
> tcg_temp_free_ptr(rb); \
> }
>
> +#define GEN_DFP_BF_I_B(name) \
> +static void gen_##name(DisasContext *ctx) \
> +{ \
> + TCGv_i32 uim; \
> + TCGv_ptr rb; \
> + if (unlikely(!ctx->fpu_enabled)) { \
> + gen_exception(ctx, POWERPC_EXCP_FPU); \
> + return; \
> + } \
> + gen_update_nip(ctx, ctx->nip - 4); \
> + uim = tcg_const_i32(UIMM5(ctx->opcode)); \
> + rb = gen_fprp_ptr(rB(ctx->opcode)); \
> + gen_helper_##name(cpu_crf[crfD(ctx->opcode)], \
> + cpu_env, uim, rb); \
> + tcg_temp_free_i32(uim); \
> + tcg_temp_free_ptr(rb); \
> +}
> +
> #define GEN_DFP_BF_A_DCM(name) \
> static void gen_##name(DisasContext *ctx) \
> { \
> @@ -8805,6 +8823,8 @@ GEN_DFP_BF_A_B(dtstex)
> GEN_DFP_BF_A_B(dtstexq)
> GEN_DFP_BF_A_B(dtstsf)
> GEN_DFP_BF_A_B(dtstsfq)
> +GEN_DFP_BF_I_B(dtstsfi)
> +GEN_DFP_BF_I_B(dtstsfiq)
> GEN_DFP_T_B_U32_U32_Rc(dquai, SIMM5, RMC)
> GEN_DFP_T_B_U32_U32_Rc(dquaiq, SIMM5, RMC)
> GEN_DFP_T_A_B_I32_Rc(dqua, RMC)
> @@ -11456,6 +11476,8 @@ GEN_DFP_BF_A_B(dtstex, 0x02, 0x05),
> GEN_DFP_BF_Ap_Bp(dtstexq, 0x02, 0x05),
> GEN_DFP_BF_A_B(dtstsf, 0x02, 0x15),
> GEN_DFP_BF_A_Bp(dtstsfq, 0x02, 0x15),
> +GEN_DFP_BF_A_B(dtstsfi, 0x03, 0x15),
> +GEN_DFP_BF_A_Bp(dtstsfiq, 0x03, 0x15),
> GEN_DFP_TE_T_B_RMC_Rc(dquai, 0x03, 0x02),
> GEN_DFP_TE_Tp_Bp_RMC_Rc(dquaiq, 0x03, 0x02),
> GEN_DFP_T_A_B_RMC_Rc(dqua, 0x03, 0x00),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 5:52 ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
` (4 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh, Sandipan Das
From: Sandipan Das <sandipandas1990@gmail.com>
Adds following instructions:
vabsdub: Vector Absolute Difference Unsigned Byte
vabsduh: Vector Absolute Difference Unsigned Halfword
vabsduw: Vector Absolute Difference Unsigned Word
Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
[ use ISA300 define and abs() ]
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 3 +++
target-ppc/int_helper.c | 23 +++++++++++++++++++++++
target-ppc/translate.c | 15 ++++++++++++---
3 files changed, 38 insertions(+), 3 deletions(-)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 68fd19e..ff6287e 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -118,6 +118,9 @@ DEF_HELPER_3(vsubudm, void, avr, avr, avr)
DEF_HELPER_3(vavgub, void, avr, avr, avr)
DEF_HELPER_3(vavguh, void, avr, avr, avr)
DEF_HELPER_3(vavguw, void, avr, avr, avr)
+DEF_HELPER_3(vabsdub, void, avr, avr, avr)
+DEF_HELPER_3(vabsduh, void, avr, avr, avr)
+DEF_HELPER_3(vabsduw, void, avr, avr, avr)
DEF_HELPER_3(vavgsb, void, avr, avr, avr)
DEF_HELPER_3(vavgsh, void, avr, avr, avr)
DEF_HELPER_3(vavgsw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 15947ad..c1b341c 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -629,6 +629,29 @@ VAVG(w, s32, int64_t, u32, uint64_t)
#undef VAVG_DO
#undef VAVG
+#define VABSDU_DO(name, element, etype) \
+void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
+{ \
+ int i; \
+ \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ r->element[i] = abs(a->element[i] - b->element[i]); \
+ } \
+}
+
+/* VABSDU - Vector absolute difference unsigned
+ * name - instruction mnemonic suffix (b: byte, h: halfword, w: word)
+ * element - element type to access from vector
+ * etype - internal data type to use for elements
+ */
+#define VABSDU(type, element, etype) \
+ VABSDU_DO(absdu##type, element, etype)
+VABSDU(b, u8, uint16_t)
+VABSDU(h, u16, uint32_t)
+VABSDU(w, u32, uint64_t)
+#undef VABSDU_DO
+#undef VABSDU
+
#define VCF(suffix, cvt, element) \
void helper_vcf##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *b, uint32_t uim) \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 23ef538..b18e13f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7373,8 +7373,17 @@ GEN_VXFORM(vminsh, 1, 13);
GEN_VXFORM(vminsw, 1, 14);
GEN_VXFORM(vminsd, 1, 15);
GEN_VXFORM(vavgub, 1, 16);
+GEN_VXFORM(vabsdub, 1, 16);
+GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
+ vabsdub, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguh, 1, 17);
+GEN_VXFORM(vabsduh, 1, 17);
+GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
+ vabsduh, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavguw, 1, 18);
+GEN_VXFORM(vabsduw, 1, 18);
+GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
+ vabsduw, PPC_NONE, PPC2_ISA300)
GEN_VXFORM(vavgsb, 1, 20);
GEN_VXFORM(vavgsh, 1, 21);
GEN_VXFORM(vavgsw, 1, 22);
@@ -10890,9 +10899,9 @@ GEN_VXFORM(vminsb, 1, 12),
GEN_VXFORM(vminsh, 1, 13),
GEN_VXFORM(vminsw, 1, 14),
GEN_VXFORM_207(vminsd, 1, 15),
-GEN_VXFORM(vavgub, 1, 16),
-GEN_VXFORM(vavguh, 1, 17),
-GEN_VXFORM(vavguw, 1, 18),
+GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE),
+GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE),
GEN_VXFORM(vavgsb, 1, 20),
GEN_VXFORM(vavgsh, 1, 21),
GEN_VXFORM(vavgsw, 1, 22),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
@ 2016-07-27 5:52 ` David Gibson
2016-07-27 6:19 ` Nikunj A Dadhania
0 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2016-07-27 5:52 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Sandipan Das
[-- Attachment #1: Type: text/plain, Size: 4632 bytes --]
On Wed, Jul 27, 2016 at 12:56:54AM +0530, Nikunj A Dadhania wrote:
> From: Sandipan Das <sandipandas1990@gmail.com>
>
> Adds following instructions:
>
> vabsdub: Vector Absolute Difference Unsigned Byte
> vabsduh: Vector Absolute Difference Unsigned Halfword
> vabsduw: Vector Absolute Difference Unsigned Word
>
> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
> [ use ISA300 define and abs() ]
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 3 +++
> target-ppc/int_helper.c | 23 +++++++++++++++++++++++
> target-ppc/translate.c | 15 ++++++++++++---
> 3 files changed, 38 insertions(+), 3 deletions(-)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 68fd19e..ff6287e 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -118,6 +118,9 @@ DEF_HELPER_3(vsubudm, void, avr, avr, avr)
> DEF_HELPER_3(vavgub, void, avr, avr, avr)
> DEF_HELPER_3(vavguh, void, avr, avr, avr)
> DEF_HELPER_3(vavguw, void, avr, avr, avr)
> +DEF_HELPER_3(vabsdub, void, avr, avr, avr)
> +DEF_HELPER_3(vabsduh, void, avr, avr, avr)
> +DEF_HELPER_3(vabsduw, void, avr, avr, avr)
> DEF_HELPER_3(vavgsb, void, avr, avr, avr)
> DEF_HELPER_3(vavgsh, void, avr, avr, avr)
> DEF_HELPER_3(vavgsw, void, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 15947ad..c1b341c 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -629,6 +629,29 @@ VAVG(w, s32, int64_t, u32, uint64_t)
> #undef VAVG_DO
> #undef VAVG
>
> +#define VABSDU_DO(name, element, etype) \
You don't appear to actually use the type parameter.
> +void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
> +{ \
> + int i; \
> + \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + r->element[i] = abs(a->element[i] - b->element[i]); \
> + } \
> +}
> +
> +/* VABSDU - Vector absolute difference unsigned
> + * name - instruction mnemonic suffix (b: byte, h: halfword, w: word)
> + * element - element type to access from vector
> + * etype - internal data type to use for elements
> + */
> +#define VABSDU(type, element, etype) \
> + VABSDU_DO(absdu##type, element, etype)
> +VABSDU(b, u8, uint16_t)
> +VABSDU(h, u16, uint32_t)
> +VABSDU(w, u32, uint64_t)
> +#undef VABSDU_DO
> +#undef VABSDU
> +
> #define VCF(suffix, cvt, element) \
> void helper_vcf##suffix(CPUPPCState *env, ppc_avr_t *r, \
> ppc_avr_t *b, uint32_t uim) \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 23ef538..b18e13f 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7373,8 +7373,17 @@ GEN_VXFORM(vminsh, 1, 13);
> GEN_VXFORM(vminsw, 1, 14);
> GEN_VXFORM(vminsd, 1, 15);
> GEN_VXFORM(vavgub, 1, 16);
> +GEN_VXFORM(vabsdub, 1, 16);
> +GEN_VXFORM_DUAL(vavgub, PPC_ALTIVEC, PPC_NONE, \
> + vabsdub, PPC_NONE, PPC2_ISA300)
> GEN_VXFORM(vavguh, 1, 17);
> +GEN_VXFORM(vabsduh, 1, 17);
> +GEN_VXFORM_DUAL(vavguh, PPC_ALTIVEC, PPC_NONE, \
> + vabsduh, PPC_NONE, PPC2_ISA300)
> GEN_VXFORM(vavguw, 1, 18);
> +GEN_VXFORM(vabsduw, 1, 18);
> +GEN_VXFORM_DUAL(vavguw, PPC_ALTIVEC, PPC_NONE, \
> + vabsduw, PPC_NONE, PPC2_ISA300)
> GEN_VXFORM(vavgsb, 1, 20);
> GEN_VXFORM(vavgsh, 1, 21);
> GEN_VXFORM(vavgsw, 1, 22);
> @@ -10890,9 +10899,9 @@ GEN_VXFORM(vminsb, 1, 12),
> GEN_VXFORM(vminsh, 1, 13),
> GEN_VXFORM(vminsw, 1, 14),
> GEN_VXFORM_207(vminsd, 1, 15),
> -GEN_VXFORM(vavgub, 1, 16),
> -GEN_VXFORM(vavguh, 1, 17),
> -GEN_VXFORM(vavguw, 1, 18),
> +GEN_VXFORM_DUAL(vavgub, vabsdub, 1, 16, PPC_ALTIVEC, PPC_NONE),
> +GEN_VXFORM_DUAL(vavguh, vabsduh, 1, 17, PPC_ALTIVEC, PPC_NONE),
> +GEN_VXFORM_DUAL(vavguw, vabsduw, 1, 18, PPC_ALTIVEC, PPC_NONE),
> GEN_VXFORM(vavgsb, 1, 20),
> GEN_VXFORM(vavgsh, 1, 21),
> GEN_VXFORM(vavgsw, 1, 22),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions
2016-07-27 5:52 ` David Gibson
@ 2016-07-27 6:19 ` Nikunj A Dadhania
0 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-27 6:19 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Sandipan Das
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:54AM +0530, Nikunj A Dadhania wrote:
>> From: Sandipan Das <sandipandas1990@gmail.com>
>>
>> Adds following instructions:
>>
>> vabsdub: Vector Absolute Difference Unsigned Byte
>> vabsduh: Vector Absolute Difference Unsigned Halfword
>> vabsduw: Vector Absolute Difference Unsigned Word
>>
>> Signed-off-by: Sandipan Das <sandipandas1990@gmail.com>
>> [ use ISA300 define and abs() ]
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target-ppc/helper.h | 3 +++
>> target-ppc/int_helper.c | 23 +++++++++++++++++++++++
>> target-ppc/translate.c | 15 ++++++++++++---
>> 3 files changed, 38 insertions(+), 3 deletions(-)
>>
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index 68fd19e..ff6287e 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -118,6 +118,9 @@ DEF_HELPER_3(vsubudm, void, avr, avr, avr)
>> DEF_HELPER_3(vavgub, void, avr, avr, avr)
>> DEF_HELPER_3(vavguh, void, avr, avr, avr)
>> DEF_HELPER_3(vavguw, void, avr, avr, avr)
>> +DEF_HELPER_3(vabsdub, void, avr, avr, avr)
>> +DEF_HELPER_3(vabsduh, void, avr, avr, avr)
>> +DEF_HELPER_3(vabsduw, void, avr, avr, avr)
>> DEF_HELPER_3(vavgsb, void, avr, avr, avr)
>> DEF_HELPER_3(vavgsh, void, avr, avr, avr)
>> DEF_HELPER_3(vavgsw, void, avr, avr, avr)
>> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> index 15947ad..c1b341c 100644
>> --- a/target-ppc/int_helper.c
>> +++ b/target-ppc/int_helper.c
>> @@ -629,6 +629,29 @@ VAVG(w, s32, int64_t, u32, uint64_t)
>> #undef VAVG_DO
>> #undef VAVG
>>
>> +#define VABSDU_DO(name, element, etype) \
>
> You don't appear to actually use the type parameter.
Right, after adding abs(), its not required.
>
>> +void helper_v##name(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b) \
>> +{ \
>> + int i; \
>> + \
>> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
>> + r->element[i] = abs(a->element[i] - b->element[i]); \
>> + } \
>> +}
>> +
>> +/* VABSDU - Vector absolute difference unsigned
>> + * name - instruction mnemonic suffix (b: byte, h: halfword, w: word)
>> + * element - element type to access from vector
>> + * etype - internal data type to use for elements
>> + */
>> +#define VABSDU(type, element, etype) \
>> + VABSDU_DO(absdu##type, element, etype)
>> +VABSDU(b, u8, uint16_t)
>> +VABSDU(h, u16, uint32_t)
>> +VABSDU(w, u32, uint64_t)
>> +#undef VABSDU_DO
>> +#undef VABSDU
>> +
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 1/6] target-ppc: add dtstsfi[q] instructions Nikunj A Dadhania
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 2/6] target-ppc: add vabsdu[b, h, w] instructions Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 5:57 ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction Nikunj A Dadhania
` (3 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh, Swapnil Bokade
From: Swapnil Bokade <bokadeswapnil@gmail.com>
Adds following instructions:
vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
vcmpnezw[.]: Vector Compare Not Equal or Zero Word
Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 6 ++++++
target-ppc/int_helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
target-ppc/translate.c | 6 ++++++
3 files changed, 61 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index ff6287e..e93b84b 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -144,6 +144,9 @@ DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
@@ -160,6 +163,9 @@ DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
+DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index c1b341c..bffe8d6 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -718,6 +718,55 @@ VCMP(gtsd, >, s64)
#undef VCMP_DO
#undef VCMP
+#define VCMPNEZ_DO(suffix, element, record) \
+void helper_vcmpnez##suffix(CPUPPCState *env, ppc_avr_t *r, \
+ ppc_avr_t *a, ppc_avr_t *b) \
+{ \
+ uint64_t ones = (uint64_t)-1; \
+ uint64_t all = ones; \
+ uint64_t none = 0; \
+ int i; \
+ \
+ for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
+ uint64_t result = ((a->element[i] == 0) \
+ || (b->element[i] == 0) \
+ || (a->element[i] != b->element[i]) ? \
+ ones : 0x0); \
+ switch (sizeof(a->element[0])) { \
+ case 8: \
+ r->u64[i] = result; \
+ break; \
+ case 4: \
+ r->u32[i] = result; \
+ break; \
+ case 2: \
+ r->u16[i] = result; \
+ break; \
+ case 1: \
+ r->u8[i] = result; \
+ break; \
+ } \
+ all &= result; \
+ none |= result; \
+ } \
+ if (record) { \
+ env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
+ } \
+}
+
+/* VCMPNEZ - Vector compare not equal to zero
+ * suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
+ * element - element type to access from vector
+ */
+#define VCMPNEZ(suffix, element) \
+ VCMPNEZ_DO(suffix, element, 0) \
+ VCMPNEZ_DO(suffix##_dot, element, 1)
+VCMPNEZ(b, u8)
+VCMPNEZ(h, u16)
+VCMPNEZ(w, u32)
+#undef VCMPNEZ_DO
+#undef VCMPNEZ
+
#define VCMPFP_DO(suffix, compare, order, record) \
void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
ppc_avr_t *a, ppc_avr_t *b) \
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index b18e13f..7cf0c8e 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7565,6 +7565,9 @@ GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
GEN_VXRFORM(vcmpequd, 3, 3)
+GEN_VXRFORM(vcmpnezb, 3, 4)
+GEN_VXRFORM(vcmpnezh, 3, 5)
+GEN_VXRFORM(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
@@ -10998,6 +11001,9 @@ GEN_VXFORM(vminfp, 5, 17),
GEN_VXRFORM(vcmpequb, 3, 0)
GEN_VXRFORM(vcmpequh, 3, 1)
GEN_VXRFORM(vcmpequw, 3, 2)
+GEN_VXRFORM(vcmpnezb, 3, 4)
+GEN_VXRFORM(vcmpnezh, 3, 5)
+GEN_VXRFORM(vcmpnezw, 3, 6)
GEN_VXRFORM(vcmpgtsb, 3, 12)
GEN_VXRFORM(vcmpgtsh, 3, 13)
GEN_VXRFORM(vcmpgtsw, 3, 14)
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
@ 2016-07-27 5:57 ` David Gibson
2016-07-27 6:22 ` Nikunj A Dadhania
0 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2016-07-27 5:57 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Swapnil Bokade
[-- Attachment #1: Type: text/plain, Size: 6626 bytes --]
On Wed, Jul 27, 2016 at 12:56:55AM +0530, Nikunj A Dadhania wrote:
> From: Swapnil Bokade <bokadeswapnil@gmail.com>
>
> Adds following instructions:
>
> vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
> vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
> vcmpnezw[.]: Vector Compare Not Equal or Zero Word
>
> Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 6 ++++++
> target-ppc/int_helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 6 ++++++
> 3 files changed, 61 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index ff6287e..e93b84b 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -144,6 +144,9 @@ DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
> @@ -160,6 +163,9 @@ DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
> +DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
> DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index c1b341c..bffe8d6 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -718,6 +718,55 @@ VCMP(gtsd, >, s64)
> #undef VCMP_DO
> #undef VCMP
>
> +#define VCMPNEZ_DO(suffix, element, record) \
> +void helper_vcmpnez##suffix(CPUPPCState *env, ppc_avr_t *r, \
> + ppc_avr_t *a, ppc_avr_t *b) \
> +{ \
> + uint64_t ones = (uint64_t)-1; \
> + uint64_t all = ones; \
> + uint64_t none = 0; \
> + int i; \
> + \
> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
> + uint64_t result = ((a->element[i] == 0) \
> + || (b->element[i] == 0) \
> + || (a->element[i] != b->element[i]) ? \
> + ones : 0x0);
> \
Couldn't you just use r->element[i] = result instead of the switch?
> + switch (sizeof(a->element[0])) { \
> + case 8: \
> + r->u64[i] = result; \
> + break;
> \
Also it doesn't actually look like there is a 64-bit case.
> + case 4: \
> + r->u32[i] = result; \
> + break; \
> + case 2: \
> + r->u16[i] = result; \
> + break; \
> + case 1: \
> + r->u8[i] = result; \
> + break; \
> + } \
> + all &= result; \
> + none |= result; \
> + } \
> + if (record) { \
> + env->crf[6] = ((all != 0) << 3) | ((none == 0) << 1); \
> + } \
> +}
> +
> +/* VCMPNEZ - Vector compare not equal to zero
> + * suffix - instruction mnemonic suffix (b: byte, h: halfword, w: word)
> + * element - element type to access from vector
> + */
> +#define VCMPNEZ(suffix, element) \
> + VCMPNEZ_DO(suffix, element, 0) \
> + VCMPNEZ_DO(suffix##_dot, element, 1)
> +VCMPNEZ(b, u8)
> +VCMPNEZ(h, u16)
> +VCMPNEZ(w, u32)
> +#undef VCMPNEZ_DO
> +#undef VCMPNEZ
> +
> #define VCMPFP_DO(suffix, compare, order, record) \
> void helper_vcmp##suffix(CPUPPCState *env, ppc_avr_t *r, \
> ppc_avr_t *a, ppc_avr_t *b) \
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index b18e13f..7cf0c8e 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7565,6 +7565,9 @@ GEN_VXRFORM(vcmpequb, 3, 0)
> GEN_VXRFORM(vcmpequh, 3, 1)
> GEN_VXRFORM(vcmpequw, 3, 2)
> GEN_VXRFORM(vcmpequd, 3, 3)
> +GEN_VXRFORM(vcmpnezb, 3, 4)
> +GEN_VXRFORM(vcmpnezh, 3, 5)
> +GEN_VXRFORM(vcmpnezw, 3, 6)
> GEN_VXRFORM(vcmpgtsb, 3, 12)
> GEN_VXRFORM(vcmpgtsh, 3, 13)
> GEN_VXRFORM(vcmpgtsw, 3, 14)
> @@ -10998,6 +11001,9 @@ GEN_VXFORM(vminfp, 5, 17),
> GEN_VXRFORM(vcmpequb, 3, 0)
> GEN_VXRFORM(vcmpequh, 3, 1)
> GEN_VXRFORM(vcmpequw, 3, 2)
> +GEN_VXRFORM(vcmpnezb, 3, 4)
> +GEN_VXRFORM(vcmpnezh, 3, 5)
> +GEN_VXRFORM(vcmpnezw, 3, 6)
> GEN_VXRFORM(vcmpgtsb, 3, 12)
> GEN_VXRFORM(vcmpgtsh, 3, 13)
> GEN_VXRFORM(vcmpgtsw, 3, 14)
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions
2016-07-27 5:57 ` David Gibson
@ 2016-07-27 6:22 ` Nikunj A Dadhania
0 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-27 6:22 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Swapnil Bokade
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:55AM +0530, Nikunj A Dadhania wrote:
>> From: Swapnil Bokade <bokadeswapnil@gmail.com>
>>
>> Adds following instructions:
>>
>> vcmpnezb[.]: Vector Compare Not Equal or Zero Byte
>> vcmpnezh[.]: Vector Compare Not Equal or Zero Halfword
>> vcmpnezw[.]: Vector Compare Not Equal or Zero Word
>>
>> Signed-off-by: Swapnil Bokade <bokadeswapnil@gmail.com>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target-ppc/helper.h | 6 ++++++
>> target-ppc/int_helper.c | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
>> target-ppc/translate.c | 6 ++++++
>> 3 files changed, 61 insertions(+)
>>
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index ff6287e..e93b84b 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -144,6 +144,9 @@ DEF_HELPER_4(vcmpequb, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequh, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequw, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequd, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezb, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezh, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezw, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtub, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtuh, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtuw, void, env, avr, avr, avr)
>> @@ -160,6 +163,9 @@ DEF_HELPER_4(vcmpequb_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequh_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequw_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpequd_dot, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezb_dot, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezh_dot, void, env, avr, avr, avr)
>> +DEF_HELPER_4(vcmpnezw_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtub_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtuh_dot, void, env, avr, avr, avr)
>> DEF_HELPER_4(vcmpgtuw_dot, void, env, avr, avr, avr)
>> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> index c1b341c..bffe8d6 100644
>> --- a/target-ppc/int_helper.c
>> +++ b/target-ppc/int_helper.c
>> @@ -718,6 +718,55 @@ VCMP(gtsd, >, s64)
>> #undef VCMP_DO
>> #undef VCMP
>>
>> +#define VCMPNEZ_DO(suffix, element, record) \
>> +void helper_vcmpnez##suffix(CPUPPCState *env, ppc_avr_t *r, \
>> + ppc_avr_t *a, ppc_avr_t *b) \
>> +{ \
>> + uint64_t ones = (uint64_t)-1; \
>> + uint64_t all = ones; \
>> + uint64_t none = 0; \
>> + int i; \
>> + \
>> + for (i = 0; i < ARRAY_SIZE(r->element); i++) { \
>> + uint64_t result = ((a->element[i] == 0) \
>> + || (b->element[i] == 0) \
>> + || (a->element[i] != b->element[i]) ? \
>> + ones : 0x0);
>> \
>
> Couldn't you just use r->element[i] = result instead of the switch?
Yes, you are right.
>> + switch (sizeof(a->element[0])) { \
>> + case 8: \
>> + r->u64[i] = result; \
>> + break;
>> \
>
> Also it doesn't actually look like there is a 64-bit case.
Right, will drop.
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
` (2 preceding siblings ...)
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 3/6] target-ppc: add vcmpnez[b, h, w][.] instructions Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 6:03 ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction Nikunj A Dadhania
` (2 subsequent siblings)
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh, Vivek Andrew Sha
From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
vslv: Vector Shift Left Variable
Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 14 ++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 17 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index e93b84b..9703f85 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
DEF_HELPER_2(lvsl, void, avr, tl)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index bffe8d6..412398f 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1708,6 +1708,20 @@ VSL(w, u32, 0x1F)
VSL(d, u64, 0x3F)
#undef VSL
+void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes, size;
+
+ size = ARRAY_SIZE(r->u8);
+ for (i = 0; i < size; i++) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = (a->u8[i] << 8) + /* extract adjacent bytes */
+ (((i + 1) < size) ? a->u8[i + 1] : 0);
+ r->u8[i] = (bytes << shift) >> 8; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 7cf0c8e..473f21a 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
+GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
GEN_VXFORM_ENV(vaddubs, 0, 8);
@@ -10942,6 +10943,7 @@ GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
+GEN_VXFORM(vslv, 2, 29),
GEN_VXFORM(vaddcuw, 0, 6),
GEN_VXFORM(vsubcuw, 0, 22),
GEN_VXFORM(vaddubs, 0, 8),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction Nikunj A Dadhania
@ 2016-07-27 6:03 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2016-07-27 6:03 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
[-- Attachment #1: Type: text/plain, Size: 2806 bytes --]
On Wed, Jul 27, 2016 at 12:56:56AM +0530, Nikunj A Dadhania wrote:
> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>
> vslv: Vector Shift Left Variable
>
> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 14 ++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 17 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index e93b84b..9703f85 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
> DEF_HELPER_3(vsld, void, avr, avr, avr)
> DEF_HELPER_3(vslo, void, avr, avr, avr)
> DEF_HELPER_3(vsro, void, avr, avr, avr)
> +DEF_HELPER_3(vslv, void, avr, avr, avr)
> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> DEF_HELPER_2(lvsl, void, avr, tl)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index bffe8d6..412398f 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -1708,6 +1708,20 @@ VSL(w, u32, 0x1F)
> VSL(d, u64, 0x3F)
> #undef VSL
>
> +void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + int i;
> + unsigned int shift, bytes, size;
> +
> + size = ARRAY_SIZE(r->u8);
> + for (i = 0; i < size; i++) {
> + shift = b->u8[i] & 0x7; /* extract shift value */
> + bytes = (a->u8[i] << 8) + /* extract adjacent bytes */
> + (((i + 1) < size) ? a->u8[i + 1] : 0);
> + r->u8[i] = (bytes << shift) >> 8; /* shift and store result */
> + }
> +}
> +
> void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
> {
> int sh = shift & 0xf;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 7cf0c8e..473f21a 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
> GEN_VXFORM(vsrad, 2, 15);
> GEN_VXFORM(vslo, 6, 16);
> GEN_VXFORM(vsro, 6, 17);
> +GEN_VXFORM(vslv, 2, 29);
> GEN_VXFORM(vaddcuw, 0, 6);
> GEN_VXFORM(vsubcuw, 0, 22);
> GEN_VXFORM_ENV(vaddubs, 0, 8);
> @@ -10942,6 +10943,7 @@ GEN_VXFORM(vsraw, 2, 14),
> GEN_VXFORM_207(vsrad, 2, 15),
> GEN_VXFORM(vslo, 6, 16),
> GEN_VXFORM(vsro, 6, 17),
> +GEN_VXFORM(vslv, 2, 29),
> GEN_VXFORM(vaddcuw, 0, 6),
> GEN_VXFORM(vsubcuw, 0, 22),
> GEN_VXFORM(vaddubs, 0, 8),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
` (3 preceding siblings ...)
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 4/6] target-ppc: add vslv instruction Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 6:05 ` David Gibson
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
2016-07-28 4:33 ` [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 David Gibson
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth
Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh, Vivek Andrew Sha
From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
Adds Vector Shift Right Variable instruction.
Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/helper.h | 1 +
target-ppc/int_helper.c | 17 +++++++++++++++++
target-ppc/translate.c | 2 ++
3 files changed, 20 insertions(+)
diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 9703f85..8eada2f 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
DEF_HELPER_3(vsld, void, avr, avr, avr)
DEF_HELPER_3(vslo, void, avr, avr, avr)
DEF_HELPER_3(vsro, void, avr, avr, avr)
+DEF_HELPER_3(vsrv, void, avr, avr, avr)
DEF_HELPER_3(vslv, void, avr, avr, avr)
DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
index 412398f..f4776f0 100644
--- a/target-ppc/int_helper.c
+++ b/target-ppc/int_helper.c
@@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
}
}
+void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
+{
+ int i;
+ unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
+
+ src[0] = 0;
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
+ src[i + 1] = a->u8[i];
+ }
+
+ for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
+ shift = b->u8[i] & 0x7; /* extract shift value */
+ bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
+ r->u8[i] = (bytes >> shift) & 0xFF; /* shift and store result */
+ }
+}
+
void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
{
int sh = shift & 0xf;
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 473f21a..3382cd0 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
GEN_VXFORM(vsrad, 2, 15);
GEN_VXFORM(vslo, 6, 16);
GEN_VXFORM(vsro, 6, 17);
+GEN_VXFORM(vsrv, 2, 28);
GEN_VXFORM(vslv, 2, 29);
GEN_VXFORM(vaddcuw, 0, 6);
GEN_VXFORM(vsubcuw, 0, 22);
@@ -10943,6 +10944,7 @@ GEN_VXFORM(vsraw, 2, 14),
GEN_VXFORM_207(vsrad, 2, 15),
GEN_VXFORM(vslo, 6, 16),
GEN_VXFORM(vsro, 6, 17),
+GEN_VXFORM(vsrv, 2, 28),
GEN_VXFORM(vslv, 2, 29),
GEN_VXFORM(vaddcuw, 0, 6),
GEN_VXFORM(vsubcuw, 0, 22),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction Nikunj A Dadhania
@ 2016-07-27 6:05 ` David Gibson
2016-07-27 6:31 ` Nikunj A Dadhania
0 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2016-07-27 6:05 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
[-- Attachment #1: Type: text/plain, Size: 2984 bytes --]
On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>
> Adds Vector Shift Right Variable instruction.
>
> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> ---
> target-ppc/helper.h | 1 +
> target-ppc/int_helper.c | 17 +++++++++++++++++
> target-ppc/translate.c | 2 ++
> 3 files changed, 20 insertions(+)
>
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index 9703f85..8eada2f 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
> DEF_HELPER_3(vsld, void, avr, avr, avr)
> DEF_HELPER_3(vslo, void, avr, avr, avr)
> DEF_HELPER_3(vsro, void, avr, avr, avr)
> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
> DEF_HELPER_3(vslv, void, avr, avr, avr)
> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 412398f..f4776f0 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> }
> }
>
> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> +{
> + int i;
> + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
> +
> + src[0] = 0;
> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> + src[i + 1] = a->u8[i];
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> + shift = b->u8[i] & 0x7; /* extract shift value */
> + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
I think you should be able to construct bytes on the fly without
pre-generating teh whole of src, as you already did for vslv.
> + r->u8[i] = (bytes >> shift) & 0xFF; /* shift and store result */
> + }
> +}
> +
> void helper_vsldoi(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, uint32_t shift)
> {
> int sh = shift & 0xf;
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 473f21a..3382cd0 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -7457,6 +7457,7 @@ GEN_VXFORM(vsraw, 2, 14);
> GEN_VXFORM(vsrad, 2, 15);
> GEN_VXFORM(vslo, 6, 16);
> GEN_VXFORM(vsro, 6, 17);
> +GEN_VXFORM(vsrv, 2, 28);
> GEN_VXFORM(vslv, 2, 29);
> GEN_VXFORM(vaddcuw, 0, 6);
> GEN_VXFORM(vsubcuw, 0, 22);
> @@ -10943,6 +10944,7 @@ GEN_VXFORM(vsraw, 2, 14),
> GEN_VXFORM_207(vsrad, 2, 15),
> GEN_VXFORM(vslo, 6, 16),
> GEN_VXFORM(vsro, 6, 17),
> +GEN_VXFORM(vsrv, 2, 28),
> GEN_VXFORM(vslv, 2, 29),
> GEN_VXFORM(vaddcuw, 0, 6),
> GEN_VXFORM(vsubcuw, 0, 22),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-27 6:05 ` David Gibson
@ 2016-07-27 6:31 ` Nikunj A Dadhania
2016-07-27 6:48 ` David Gibson
0 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-27 6:31 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
>> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>>
>> Adds Vector Shift Right Variable instruction.
>>
>> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> ---
>> target-ppc/helper.h | 1 +
>> target-ppc/int_helper.c | 17 +++++++++++++++++
>> target-ppc/translate.c | 2 ++
>> 3 files changed, 20 insertions(+)
>>
>> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> index 9703f85..8eada2f 100644
>> --- a/target-ppc/helper.h
>> +++ b/target-ppc/helper.h
>> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
>> DEF_HELPER_3(vsld, void, avr, avr, avr)
>> DEF_HELPER_3(vslo, void, avr, avr, avr)
>> DEF_HELPER_3(vsro, void, avr, avr, avr)
>> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
>> DEF_HELPER_3(vslv, void, avr, avr, avr)
>> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
>> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
>> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> index 412398f..f4776f0 100644
>> --- a/target-ppc/int_helper.c
>> +++ b/target-ppc/int_helper.c
>> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>> }
>> }
>>
>> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>> +{
>> + int i;
>> + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
>> +
>> + src[0] = 0;
>> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
>> + src[i + 1] = a->u8[i];
>> + }
>> +
>> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
>> + shift = b->u8[i] & 0x7; /* extract shift value */
>> + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
>
> I think you should be able to construct bytes on the fly without
> pre-generating teh whole of src, as you already did for vslv.
Had done that, but that introduces a bug like this, for eg:
vslv vra,vra,vrb
So modified vra->u8[i] is used during subsequent operation as input.
Assuming I take care or special casing "0":
bytes = ((vra->u8[i - 1] << 8) | (vra->u8[i]))
vra->u8[i] = (bytes >> shift) & 0xFF;
when i = 1, bytes will ((vra->u8[0] << 8) | (vra->u8[1])). But vra->u8[0],
was changed in the previous operation.
Thats the reason src[] is needed
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-27 6:31 ` Nikunj A Dadhania
@ 2016-07-27 6:48 ` David Gibson
2016-07-27 6:57 ` Nikunj A Dadhania
0 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2016-07-27 6:48 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
[-- Attachment #1: Type: text/plain, Size: 3071 bytes --]
On Wed, Jul 27, 2016 at 12:01:33PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> >> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> >>
> >> Adds Vector Shift Right Variable instruction.
> >>
> >> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> ---
> >> target-ppc/helper.h | 1 +
> >> target-ppc/int_helper.c | 17 +++++++++++++++++
> >> target-ppc/translate.c | 2 ++
> >> 3 files changed, 20 insertions(+)
> >>
> >> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> >> index 9703f85..8eada2f 100644
> >> --- a/target-ppc/helper.h
> >> +++ b/target-ppc/helper.h
> >> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
> >> DEF_HELPER_3(vsld, void, avr, avr, avr)
> >> DEF_HELPER_3(vslo, void, avr, avr, avr)
> >> DEF_HELPER_3(vsro, void, avr, avr, avr)
> >> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
> >> DEF_HELPER_3(vslv, void, avr, avr, avr)
> >> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> >> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> >> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> >> index 412398f..f4776f0 100644
> >> --- a/target-ppc/int_helper.c
> >> +++ b/target-ppc/int_helper.c
> >> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> >> }
> >> }
> >>
> >> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> >> +{
> >> + int i;
> >> + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
> >> +
> >> + src[0] = 0;
> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> >> + src[i + 1] = a->u8[i];
> >> + }
> >> +
> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> >> + shift = b->u8[i] & 0x7; /* extract shift value */
> >> + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
> >
> > I think you should be able to construct bytes on the fly without
> > pre-generating teh whole of src, as you already did for vslv.
>
> Had done that, but that introduces a bug like this, for eg:
>
> vslv vra,vra,vrb
>
> So modified vra->u8[i] is used during subsequent operation as input.
>
> Assuming I take care or special casing "0":
>
> bytes = ((vra->u8[i - 1] << 8) | (vra->u8[i]))
> vra->u8[i] = (bytes >> shift) & 0xFF;
>
> when i = 1, bytes will ((vra->u8[0] << 8) | (vra->u8[1])). But vra->u8[0],
> was changed in the previous operation.
Ah, good point.
> Thats the reason src[] is needed
It's probably possible to avoid generating all of src by instead
generating the bytes one loop iteration ahead, but that sounds fiddly,
so the current approach is fine for now.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-27 6:48 ` David Gibson
@ 2016-07-27 6:57 ` Nikunj A Dadhania
2016-07-27 7:02 ` David Gibson
0 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-27 6:57 UTC (permalink / raw)
To: David Gibson
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:01:33PM +0530, Nikunj A Dadhania wrote:
>> David Gibson <david@gibson.dropbear.id.au> writes:
>>
>> > [ Unknown signature status ]
>> > On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
>> >> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>> >>
>> >> Adds Vector Shift Right Variable instruction.
>> >>
>> >> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
>> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
>> >> ---
>> >> target-ppc/helper.h | 1 +
>> >> target-ppc/int_helper.c | 17 +++++++++++++++++
>> >> target-ppc/translate.c | 2 ++
>> >> 3 files changed, 20 insertions(+)
>> >>
>> >> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
>> >> index 9703f85..8eada2f 100644
>> >> --- a/target-ppc/helper.h
>> >> +++ b/target-ppc/helper.h
>> >> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
>> >> DEF_HELPER_3(vsld, void, avr, avr, avr)
>> >> DEF_HELPER_3(vslo, void, avr, avr, avr)
>> >> DEF_HELPER_3(vsro, void, avr, avr, avr)
>> >> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
>> >> DEF_HELPER_3(vslv, void, avr, avr, avr)
>> >> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
>> >> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
>> >> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
>> >> index 412398f..f4776f0 100644
>> >> --- a/target-ppc/int_helper.c
>> >> +++ b/target-ppc/int_helper.c
>> >> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>> >> }
>> >> }
>> >>
>> >> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
>> >> +{
>> >> + int i;
>> >> + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
>> >> +
>> >> + src[0] = 0;
>> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
>> >> + src[i + 1] = a->u8[i];
>> >> + }
>> >> +
>> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
>> >> + shift = b->u8[i] & 0x7; /* extract shift value */
>> >> + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
>> >
>> > I think you should be able to construct bytes on the fly without
>> > pre-generating teh whole of src, as you already did for vslv.
>>
>> Had done that, but that introduces a bug like this, for eg:
>>
>> vslv vra,vra,vrb
>>
>> So modified vra->u8[i] is used during subsequent operation as input.
>>
>> Assuming I take care or special casing "0":
>>
>> bytes = ((vra->u8[i - 1] << 8) | (vra->u8[i]))
>> vra->u8[i] = (bytes >> shift) & 0xFF;
>>
>> when i = 1, bytes will ((vra->u8[0] << 8) | (vra->u8[1])). But vra->u8[0],
>> was changed in the previous operation.
>
> Ah, good point.
>
>> Thats the reason src[] is needed
>
> It's probably possible to avoid generating all of src by instead
> generating the bytes one loop iteration ahead, but that sounds fiddly,
> so the current approach is fine for now.
Or do the operation in the reverse: starting from size to 0. Let me try
that.
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction
2016-07-27 6:57 ` Nikunj A Dadhania
@ 2016-07-27 7:02 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2016-07-27 7:02 UTC (permalink / raw)
To: Nikunj A Dadhania
Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh,
Vivek Andrew Sha
[-- Attachment #1: Type: text/plain, Size: 3581 bytes --]
On Wed, Jul 27, 2016 at 12:27:27PM +0530, Nikunj A Dadhania wrote:
> David Gibson <david@gibson.dropbear.id.au> writes:
>
> > [ Unknown signature status ]
> > On Wed, Jul 27, 2016 at 12:01:33PM +0530, Nikunj A Dadhania wrote:
> >> David Gibson <david@gibson.dropbear.id.au> writes:
> >>
> >> > [ Unknown signature status ]
> >> > On Wed, Jul 27, 2016 at 12:56:57AM +0530, Nikunj A Dadhania wrote:
> >> >> From: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> >> >>
> >> >> Adds Vector Shift Right Variable instruction.
> >> >>
> >> >> Signed-off-by: Vivek Andrew Sha <vivekandrewsha@gmail.com>
> >> >> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
> >> >> ---
> >> >> target-ppc/helper.h | 1 +
> >> >> target-ppc/int_helper.c | 17 +++++++++++++++++
> >> >> target-ppc/translate.c | 2 ++
> >> >> 3 files changed, 20 insertions(+)
> >> >>
> >> >> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> >> >> index 9703f85..8eada2f 100644
> >> >> --- a/target-ppc/helper.h
> >> >> +++ b/target-ppc/helper.h
> >> >> @@ -211,6 +211,7 @@ DEF_HELPER_3(vslw, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vsld, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vslo, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vsro, void, avr, avr, avr)
> >> >> +DEF_HELPER_3(vsrv, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vslv, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vaddcuw, void, avr, avr, avr)
> >> >> DEF_HELPER_3(vsubcuw, void, avr, avr, avr)
> >> >> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> >> >> index 412398f..f4776f0 100644
> >> >> --- a/target-ppc/int_helper.c
> >> >> +++ b/target-ppc/int_helper.c
> >> >> @@ -1722,6 +1722,23 @@ void helper_vslv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> >> >> }
> >> >> }
> >> >>
> >> >> +void helper_vsrv(ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)
> >> >> +{
> >> >> + int i;
> >> >> + unsigned int shift, bytes, src[ARRAY_SIZE(r->u8) + 1];
> >> >> +
> >> >> + src[0] = 0;
> >> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> >> >> + src[i + 1] = a->u8[i];
> >> >> + }
> >> >> +
> >> >> + for (i = 0; i < ARRAY_SIZE(r->u8); i++) {
> >> >> + shift = b->u8[i] & 0x7; /* extract shift value */
> >> >> + bytes = (src[i] << 8) + src[i + 1]; /* extract adjacent bytes */
> >> >
> >> > I think you should be able to construct bytes on the fly without
> >> > pre-generating teh whole of src, as you already did for vslv.
> >>
> >> Had done that, but that introduces a bug like this, for eg:
> >>
> >> vslv vra,vra,vrb
> >>
> >> So modified vra->u8[i] is used during subsequent operation as input.
> >>
> >> Assuming I take care or special casing "0":
> >>
> >> bytes = ((vra->u8[i - 1] << 8) | (vra->u8[i]))
> >> vra->u8[i] = (bytes >> shift) & 0xFF;
> >>
> >> when i = 1, bytes will ((vra->u8[0] << 8) | (vra->u8[1])). But vra->u8[0],
> >> was changed in the previous operation.
> >
> > Ah, good point.
> >
> >> Thats the reason src[] is needed
> >
> > It's probably possible to avoid generating all of src by instead
> > generating the bytes one loop iteration ahead, but that sounds fiddly,
> > so the current approach is fine for now.
>
> Or do the operation in the reverse: starting from size to 0. Let me try
> that.
Good idea, that should work.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
` (4 preceding siblings ...)
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 5/6] target-ppc: add vsrv instruction Nikunj A Dadhania
@ 2016-07-26 19:26 ` Nikunj A Dadhania
2016-07-27 6:07 ` David Gibson
2016-07-28 4:33 ` [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 David Gibson
6 siblings, 1 reply; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-26 19:26 UTC (permalink / raw)
To: qemu-ppc, david, rth; +Cc: qemu-devel, nikunj, bharata, aneesh.kumar, benh
extswsli : Extend Sign Word & Shift Left Immediate
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
---
target-ppc/translate.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 3382cd0..0a1b750 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2322,6 +2322,32 @@ static void gen_sradi1(DisasContext *ctx)
gen_sradi(ctx, 1);
}
+/* extswsli & extswsli. */
+static inline void gen_extswsli(DisasContext *ctx, int n)
+{
+ int sh = SH(ctx->opcode) + (n << 5);
+ TCGv dst = cpu_gpr[rA(ctx->opcode)];
+ TCGv src = cpu_gpr[rS(ctx->opcode)];
+
+ tcg_gen_ext32s_tl(dst, src);
+ if (sh != 0) {
+ tcg_gen_shli_tl(dst, dst, sh);
+ }
+ if (unlikely(Rc(ctx->opcode) != 0)) {
+ gen_set_Rc0(ctx, dst);
+ }
+}
+
+static void gen_extswsli0(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 0);
+}
+
+static void gen_extswsli1(DisasContext *ctx)
+{
+ gen_extswsli(ctx, 1);
+}
+
/* srd & srd. */
static void gen_srd(DisasContext *ctx)
{
@@ -10231,6 +10257,10 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
+GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
+GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
+ PPC_NONE, PPC2_ISA300),
#endif
GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
--
2.7.4
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
@ 2016-07-27 6:07 ` David Gibson
0 siblings, 0 replies; 21+ messages in thread
From: David Gibson @ 2016-07-27 6:07 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh
[-- Attachment #1: Type: text/plain, Size: 2225 bytes --]
On Wed, Jul 27, 2016 at 12:56:58AM +0530, Nikunj A Dadhania wrote:
> extswsli : Extend Sign Word & Shift Left Immediate
>
> Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
> ---
> target-ppc/translate.c | 30 ++++++++++++++++++++++++++++++
> 1 file changed, 30 insertions(+)
>
> diff --git a/target-ppc/translate.c b/target-ppc/translate.c
> index 3382cd0..0a1b750 100644
> --- a/target-ppc/translate.c
> +++ b/target-ppc/translate.c
> @@ -2322,6 +2322,32 @@ static void gen_sradi1(DisasContext *ctx)
> gen_sradi(ctx, 1);
> }
>
> +/* extswsli & extswsli. */
> +static inline void gen_extswsli(DisasContext *ctx, int n)
> +{
> + int sh = SH(ctx->opcode) + (n << 5);
> + TCGv dst = cpu_gpr[rA(ctx->opcode)];
> + TCGv src = cpu_gpr[rS(ctx->opcode)];
> +
> + tcg_gen_ext32s_tl(dst, src);
> + if (sh != 0) {
> + tcg_gen_shli_tl(dst, dst, sh);
> + }
> + if (unlikely(Rc(ctx->opcode) != 0)) {
> + gen_set_Rc0(ctx, dst);
> + }
> +}
> +
> +static void gen_extswsli0(DisasContext *ctx)
> +{
> + gen_extswsli(ctx, 0);
> +}
> +
> +static void gen_extswsli1(DisasContext *ctx)
> +{
> + gen_extswsli(ctx, 1);
> +}
> +
> /* srd & srd. */
> static void gen_srd(DisasContext *ctx)
> {
> @@ -10231,6 +10257,10 @@ GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
> GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
> GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
> GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
> +GEN_HANDLER2_E(extswsli0, "extswsli", 0x1F, 0x1A, 0x1B, 0x00000000,
> + PPC_NONE, PPC2_ISA300),
> +GEN_HANDLER2_E(extswsli1, "extswsli", 0x1F, 0x1B, 0x1B, 0x00000000,
> + PPC_NONE, PPC2_ISA300),
> #endif
> GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
> GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2
2016-07-26 19:26 [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 Nikunj A Dadhania
` (5 preceding siblings ...)
2016-07-26 19:26 ` [Qemu-devel] [PATCH RFC v0 6/6] target-ppc: add extswsli[.] instruction Nikunj A Dadhania
@ 2016-07-28 4:33 ` David Gibson
2016-07-28 6:06 ` Nikunj A Dadhania
6 siblings, 1 reply; 21+ messages in thread
From: David Gibson @ 2016-07-28 4:33 UTC (permalink / raw)
To: Nikunj A Dadhania; +Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh
[-- Attachment #1: Type: text/plain, Size: 1931 bytes --]
On Wed, Jul 27, 2016 at 12:56:52AM +0530, Nikunj A Dadhania wrote:
> This series contains 11 new instructions for POWER9 described in ISA3.0.
>
> Patches:
> 01: dtstsfi[q] : DFP Test Significance Immediate [Quad]
> 02: vabsdub : Vector Absolute Difference Unsigned Byte
> vabsduh : Vector Absolute Difference Unsigned Halfword
> vabsduw : Vector Absolute Difference Unsigned Word
> 03: vcmpnezb[.] : Vector Compare Not Equal or Zero Byte
> vcmpnezh[.] : Vector Compare Not Equal or Zero Halfword
> vcmpnezw[.] : Vector Compare Not Equal or Zero Word
> 04: vslv : Vector Shift Left Variable
> 05: vsrv : Vector Shift Right Variable
> 06: extswsli : Extend Sign Word & Shift Left Immediate
>
> Both part1 and part2 pushed here:
> https://github.com/nikunjad/qemu/tree/p9-tcg
I'm hoping to get an ack from rth before merging these. At the very
least they'll need a rebase on top of BenH's big patch series which I
merged into ppc-for-2.8.
>
> Nikunj A Dadhania (1):
> target-ppc: add extswsli[.] instruction
>
> Sandipan Das (2):
> target-ppc: add dtstsfi[q] instructions
> target-ppc: add vabsdu[b,h,w] instructions
>
> Swapnil Bokade (1):
> target-ppc: add vcmpnez[b,h,w][.] instructions
>
> Vivek Andrew Sha (2):
> target-ppc: add vslv instruction
> target-ppc: add vsrv instruction
>
> target-ppc/dfp_helper.c | 35 ++++++++++++++++
> target-ppc/helper.h | 13 ++++++
> target-ppc/int_helper.c | 103 ++++++++++++++++++++++++++++++++++++++++++++++++
> target-ppc/translate.c | 77 ++++++++++++++++++++++++++++++++++--
> 4 files changed, 225 insertions(+), 3 deletions(-)
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2
2016-07-28 4:33 ` [Qemu-devel] [PATCH RFC v0 0/6] POWER9 TCG enablements - part2 David Gibson
@ 2016-07-28 6:06 ` Nikunj A Dadhania
0 siblings, 0 replies; 21+ messages in thread
From: Nikunj A Dadhania @ 2016-07-28 6:06 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, rth, qemu-devel, bharata, aneesh.kumar, benh
David Gibson <david@gibson.dropbear.id.au> writes:
> [ Unknown signature status ]
> On Wed, Jul 27, 2016 at 12:56:52AM +0530, Nikunj A Dadhania wrote:
>> This series contains 11 new instructions for POWER9 described in ISA3.0.
>>
>> Patches:
>> 01: dtstsfi[q] : DFP Test Significance Immediate [Quad]
>> 02: vabsdub : Vector Absolute Difference Unsigned Byte
>> vabsduh : Vector Absolute Difference Unsigned Halfword
>> vabsduw : Vector Absolute Difference Unsigned Word
>> 03: vcmpnezb[.] : Vector Compare Not Equal or Zero Byte
>> vcmpnezh[.] : Vector Compare Not Equal or Zero Halfword
>> vcmpnezw[.] : Vector Compare Not Equal or Zero Word
>> 04: vslv : Vector Shift Left Variable
>> 05: vsrv : Vector Shift Right Variable
>> 06: extswsli : Extend Sign Word & Shift Left Immediate
>>
>> Both part1 and part2 pushed here:
>> https://github.com/nikunjad/qemu/tree/p9-tcg
>
> I'm hoping to get an ack from rth before merging these. At the very
> least they'll need a rebase on top of BenH's big patch series which I
> merged into ppc-for-2.8.
I have part2 rebased on benh's wip series addressing your comments. I
was waiting for that to get in, will rebase on ppc-for-2.8 and send v2.
Are you planning to pull div[dw] from part1, otherwise will put in part2
and send.
Regards
Nikunj
^ permalink raw reply [flat|nested] 21+ messages in thread