From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:33222) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bSIPv-0008V2-Iz for qemu-devel@nongnu.org; Wed, 27 Jul 2016 02:34:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bSIPs-0007XI-1G for qemu-devel@nongnu.org; Wed, 27 Jul 2016 02:34:07 -0400 Date: Wed, 27 Jul 2016 16:29:13 +1000 From: David Gibson Message-ID: <20160727062913.GP17429@voom.fritz.box> References: <1469534318-5549-1-git-send-email-nikunj@linux.vnet.ibm.com> <1469534318-5549-8-git-send-email-nikunj@linux.vnet.ibm.com> <20160727051904.GE17429@voom.fritz.box> <87eg6fbo5w.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="Vj8lTl3Roa4E9STX" Content-Disposition: inline In-Reply-To: <87eg6fbo5w.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Subject: Re: [Qemu-devel] [PATCH v4 07/15] target-ppc: implement branch-less divw[o][.] List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org, bharata@linux.vnet.ibm.com, aneesh.kumar@linux.vnet.ibm.com --Vj8lTl3Roa4E9STX Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Jul 27, 2016 at 11:47:15AM +0530, Nikunj A Dadhania wrote: > David Gibson writes: >=20 > > [ Unknown signature status ] > > On Tue, Jul 26, 2016 at 05:28:30PM +0530, Nikunj A Dadhania wrote: > >> While implementing modulo instructions figured out that the > >> implementation uses many branches. Change the logic to achieve the > >> branch-less code. Undefined value is set to dividend in case of invalid > >> input. > >>=20 > >> Signed-off-by: Nikunj A Dadhania > >> --- > >> target-ppc/translate.c | 48 +++++++++++++++++++++++------------------= ------- > >> 1 file changed, 23 insertions(+), 25 deletions(-) > >>=20 > >> diff --git a/target-ppc/translate.c b/target-ppc/translate.c > >> index 7c7328f..69d9ae0 100644 > >> --- a/target-ppc/translate.c > >> +++ b/target-ppc/translate.c > >> @@ -1049,41 +1049,39 @@ static void gen_addpcis(DisasContext *ctx) > >> static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCG= v arg1, > >> TCGv arg2, int sign, int compute= _ov) > >> { > >> - TCGLabel *l1 =3D gen_new_label(); > >> - TCGLabel *l2 =3D gen_new_label(); > >> - TCGv_i32 t0 =3D tcg_temp_local_new_i32(); > >> - TCGv_i32 t1 =3D tcg_temp_local_new_i32(); > >> + TCGv_i32 t0 =3D tcg_temp_new_i32(); > >> + TCGv_i32 t1 =3D tcg_temp_new_i32(); > >> + TCGv_i32 t2 =3D tcg_temp_new_i32(); > >> + TCGv_i32 t3 =3D tcg_temp_new_i32(); > >> =20 > >> tcg_gen_trunc_tl_i32(t0, arg1); > >> tcg_gen_trunc_tl_i32(t1, arg2); > >> - tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1); > >> - if (sign) { > >> - TCGLabel *l3 =3D gen_new_label(); > >> - tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3); > >> - tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1); > >> - gen_set_label(l3); > >> - tcg_gen_div_i32(t0, t0, t1); > >> - } else { > >> - tcg_gen_divu_i32(t0, t0, t1); > >> - } > >> - if (compute_ov) { > >> - tcg_gen_movi_tl(cpu_ov, 0); > >> - } > >> - tcg_gen_br(l2); > >> - gen_set_label(l1); > >> if (sign) { > >> - tcg_gen_sari_i32(t0, t0, 31); > >> + tcg_gen_setcondi_i32(TCG_COND_EQ, t2, t0, INT_MIN); > >> + tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, -1); > >> + tcg_gen_and_i32(t2, t2, t3); > >> + tcg_gen_setcondi_i32(TCG_COND_EQ, t3, t1, 0); > >> + tcg_gen_or_i32(t2, t2, t3); > >> + tcg_gen_movi_i32(t3, 0); > >> + tcg_gen_movcond_i32(TCG_COND_NE, t1, t2, t3, t2, t1); > >> + tcg_gen_div_i32(t3, t0, t1); > >> + tcg_gen_extu_i32_tl(ret, t3); > > > > Should this be a signed extend, given it's a signed divide? >=20 > Don't think so, as the instruction is 32-bit, caller will only look at > the 32bit and div_i32 is signed, it will take care of extending sign > till 32-boundary. Hrm. I thought most 32-bit arithmetic operations on Power actually set the underlying 64-bit registers to a sign extended version of the 32-bit result. --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --Vj8lTl3Roa4E9STX Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAEBAgAGBQJXmFS4AAoJEGw4ysog2bOS3UgP/iJbIyQoyvNMik8IR4112b2g vynlX/8k/G2KWAivNtXC7UFoV4nw5B+1OqedWQSEZKl7ufA7Wi/Qw/W2zvlPiuP6 EcwODZvLD03fbRENNZsaLReIIAcBuFKASQ8iWjmc9B7rS1sG94zG93lUP+Ha6uv2 HpSPnNb9h1bENU3nItIts+aaQUKery5jbNZuXMF+ka8wH5eseDKHG2sC9Ycs65HT HeAzhvExkQOWBn8ka+g2ksCdPVae16LNoxq4GijfHMeUn9dYJ1gAs3dVhpxAQrK4 lsHEuo7rsmpZY/r23Nf9SxR41RG4aaHX9cNo1+SqXJd6GLzNsZa+ppPYB5AmPcA0 1sJ6TrlSCMw5xRa3DdyuosDoTPTmeu2k0epv7SHYTyXCGqbtN6W+Z6JA4xl/bbEX 3cJgz4NcREhXNkqGt03DR9xSMG9TcXwjG0m6M07+OP0ZMRtocZByeSDrK0xbdaXn cRk64BZFmBkIX3iiKZ2Jg43OdzYrEjKgdPAKyfZxjrkWPiq9Ji/EopNQQAdO38Qh Rguw/s7UZGGAFyrlsXvG9coOhdIwblNUUXbpYCkDEK2Dz0OyrjzygBDWMexnyTOO NC3kvDDNPvCGjxAZOoDGff8NarYQVyXYc+phzDrXKsPyJr8kWvdg6QtZLAbzhLsO FRb6IoPXs31kZSH+e2z+ =rpPR -----END PGP SIGNATURE----- --Vj8lTl3Roa4E9STX--