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From: David Gibson <david@gibson.dropbear.id.au>
To: alarson@ddci.com
Cc: agraf@suse.de, qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Subject: Re: [Qemu-devel] target-ppc: SPR_BOOKE_ESR not set on FP exceptions
Date: Mon, 1 Aug 2016 14:35:43 +1000	[thread overview]
Message-ID: <20160801043543.GW2588@voom.fritz.box> (raw)
In-Reply-To: <OFE8303EB4.3E78490C-ON86257FFF.00474BB9-86257FFF.0047C8F7@ddci.com>

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On Fri, Jul 29, 2016 at 08:04:04AM -0500, alarson@ddci.com wrote:
> David Gibson <david@gibson.dropbear.id.au> wrote on 07/29/2016 12:40:15 
> AM:
> 
> > From: David Gibson <david@gibson.dropbear.id.au>
> > To: alarson@ddci.com
> > Cc: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, agraf@suse.de
> > Date: 07/29/2016 12:38 AM
> > Subject: Re: target-ppc: SPR_BOOKE_ESR not set on FP exceptions
> > 
> > On Thu, Jul 28, 2016 at 06:32:27PM -0500, alarson@ddci.com wrote:
> ...
> > > I did a quick check of the bits set in the POWERPC_EXCP_PROGRAM case.
> > > The classic PPC sets SRR1 bits 11--15 depending on the exception.  In
> > > Book E these correspond to bits 43--47,
> > 
> > Um.. what?  I'm not understanding where this bit shift is coming
> > from. 
> 
> Sorry, I was looking at an old "classic" 32-bit manual for the SRR1 
> exception definition and a 64-bit manual for the BookE.  They are
> the same bits.  MSB0 bit numbering bytes again :-)

Ok.  Can you re-do your analysis and submit a patch to fix this?

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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      reply	other threads:[~2016-08-01  4:34 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-07-28 23:32 [Qemu-devel] target-ppc: SPR_BOOKE_ESR not set on FP exceptions alarson
2016-07-29  5:40 ` David Gibson
2016-07-29 13:04   ` alarson
2016-08-01  4:35     ` David Gibson [this message]

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