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From: David Gibson <david@gibson.dropbear.id.au>
To: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org,
	nikunj@linux.vnet.ibm.com, benh@kernel.crashing.org
Subject: Re: [Qemu-devel] [PATCH v3 5/5] target-ppc: add vector permute right indexed instruction
Date: Tue, 16 Aug 2016 14:45:31 +1000	[thread overview]
Message-ID: <20160816044530.GI14530@voom.fritz.box> (raw)
In-Reply-To: <1470901008-3284-6-git-send-email-raji@linux.vnet.ibm.com>

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On Thu, Aug 11, 2016 at 01:06:48PM +0530, Rajalakshmi Srinivasaraghavan wrote:
> Add vpermr instruction from ISA 3.0.
> 
> Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
> ---
>  target-ppc/helper.h             |    1 +
>  target-ppc/int_helper.c         |   23 +++++++++++++++++++++++
>  target-ppc/translate/vmx-impl.c |   18 ++++++++++++++++++
>  target-ppc/translate/vmx-ops.c  |    1 +
>  4 files changed, 43 insertions(+), 0 deletions(-)
> 
> diff --git a/target-ppc/helper.h b/target-ppc/helper.h
> index d1d9418..3c476c9 100644
> --- a/target-ppc/helper.h
> +++ b/target-ppc/helper.h
> @@ -270,6 +270,7 @@ DEF_HELPER_5(vmsumubm, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vmsummbm, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vsel, void, env, avr, avr, avr, avr)
>  DEF_HELPER_5(vperm, void, env, avr, avr, avr, avr)
> +DEF_HELPER_5(vpermr, void, env, avr, avr, avr, avr)
>  DEF_HELPER_4(vpkshss, void, env, avr, avr, avr)
>  DEF_HELPER_4(vpkshus, void, env, avr, avr, avr)
>  DEF_HELPER_4(vpkswss, void, env, avr, avr, avr)
> diff --git a/target-ppc/int_helper.c b/target-ppc/int_helper.c
> index 6bed3b6..a35355f 100644
> --- a/target-ppc/int_helper.c
> +++ b/target-ppc/int_helper.c
> @@ -1126,6 +1126,29 @@ void helper_vperm(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
>      *r = result;
>  }
>  
> +void helper_vpermr(CPUPPCState *env, ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b,
> +                  ppc_avr_t *c)
> +{
> +    ppc_avr_t result;
> +    int i;
> +
> +    VECTOR_FOR_INORDER_I(i, u8) {
> +        int s = c->u8[i] & 0x1f;
> +#if defined(HOST_WORDS_BIGENDIAN)
> +        int index = 15 - (s & 0xf);
> +#else
> +        int index = s & 0xf;
> +#endif
> +
> +        if (s & 0x10) {
> +            result.u8[i] = a->u8[index];
> +        } else {
> +            result.u8[i] = b->u8[index];
> +        }
> +    }
> +    *r = result;
> +}
> +
>  #if defined(HOST_WORDS_BIGENDIAN)
>  #define VBPERMQ_INDEX(avr, i) ((avr)->u8[(i)])
>  #define VBPERMQ_DW(index) (((index) & 0x40) != 0)
> diff --git a/target-ppc/translate/vmx-impl.c b/target-ppc/translate/vmx-impl.c
> index 38f8ad7..feb10de 100644
> --- a/target-ppc/translate/vmx-impl.c
> +++ b/target-ppc/translate/vmx-impl.c
> @@ -750,6 +750,24 @@ static void gen_vmladduhm(DisasContext *ctx)
>      tcg_temp_free_ptr(rd);
>  }
>  
> +static void gen_vpermr(DisasContext *ctx)
> +{
> +    TCGv_ptr ra, rb, rc, rd;
> +    if (unlikely(!ctx->altivec_enabled)) {
> +        gen_exception(ctx, POWERPC_EXCP_VPU);
> +        return;
> +    }
> +    ra = gen_avr_ptr(rA(ctx->opcode));
> +    rb = gen_avr_ptr(rB(ctx->opcode));
> +    rc = gen_avr_ptr(rC(ctx->opcode));
> +    rd = gen_avr_ptr(rD(ctx->opcode));
> +    gen_helper_vpermr(cpu_env, rd, ra, rb, rc);
> +    tcg_temp_free_ptr(ra);
> +    tcg_temp_free_ptr(rb);
> +    tcg_temp_free_ptr(rc);
> +    tcg_temp_free_ptr(rd);
> +}

Why do you need this gen_vpermr() function while there isn't a
matching gen_vperm()?

> +
>  GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
>  GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
>  GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
> diff --git a/target-ppc/translate/vmx-ops.c b/target-ppc/translate/vmx-ops.c
> index 32bd533..ad72db5 100644
> --- a/target-ppc/translate/vmx-ops.c
> +++ b/target-ppc/translate/vmx-ops.c
> @@ -219,6 +219,7 @@ GEN_VXFORM_300_EO(vctzb, 0x01, 0x18, 0x1C),
>  GEN_VXFORM_300_EO(vctzh, 0x01, 0x18, 0x1D),
>  GEN_VXFORM_300_EO(vctzw, 0x01, 0x18, 0x1E),
>  GEN_VXFORM_300_EO(vctzd, 0x01, 0x18, 0x1F),
> +GEN_VXFORM_300(vpermr, 0x1D, 0xFF),
>  
>  #define GEN_VXFORM_NOA(name, opc2, opc3)                                \
>      GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)

-- 
David Gibson			| I'll have my music baroque, and my code
david AT gibson.dropbear.id.au	| minimalist, thank you.  NOT _the_ _other_
				| _way_ _around_!
http://www.ozlabs.org/~dgibson

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  reply	other threads:[~2016-08-16  4:45 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-11  7:36 [Qemu-devel] [PATCH v3 0/5] POWER9 TCG enablement - part3 Rajalakshmi Srinivasaraghavan
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 1/5] target-ppc: add vector insert instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:18   ` David Gibson
2016-08-19  5:46     ` Rajalakshmi Srinivasaraghavan
2016-08-23 15:08       ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 2/5] target-ppc: add vector extract instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:21   ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 3/5] target-ppc: add vector count trailing zeros instructions Rajalakshmi Srinivasaraghavan
2016-08-16  4:46   ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 4/5] target-ppc: add vector bit permute doubleword instruction Rajalakshmi Srinivasaraghavan
2016-08-16  4:33   ` David Gibson
2016-08-11  7:36 ` [Qemu-devel] [PATCH v3 5/5] target-ppc: add vector permute right indexed instruction Rajalakshmi Srinivasaraghavan
2016-08-16  4:45   ` David Gibson [this message]
2016-08-16 10:14     ` Rajalakshmi Srinivasaraghavan

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