Re: [Qemu-devel] [PATCH 0/9] target-mips: Add Enhanced Virtual Addressing (EVA) support

[no-reply@patchew.org]

Hi,

Your series seems to have some coding style problems. See output below for
more information:

Subject: [Qemu-devel] [PATCH 0/9] target-mips: Add Enhanced Virtual Addressing (EVA) support
Type: series
Message-id: cover.bcfb6a7121f5fd92c9ebda9f199ff06cb0d4bc05.1473159543.git-series.james.hogan@imgtec.com

=== TEST SCRIPT BEGIN ===
#!/bin/bash

BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0

# Useful git options
git config --local diff.renamelimit 0
git config --local diff.renames True

commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
    echo "Checking PATCH $n/$total: $(git show --no-patch --format=%s $c)..."
    if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
        failed=1
        echo
    fi
    n=$((n+1))
done

exit $failed
=== TEST SCRIPT END ===

Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
 * [new tag]         patchew/cover.bcfb6a7121f5fd92c9ebda9f199ff06cb0d4bc05.1473159543.git-series.james.hogan@imgtec.com -> patchew/cover.bcfb6a7121f5fd92c9ebda9f199ff06cb0d4bc05.1473159543.git-series.james.hogan@imgtec.com
Switched to a new branch 'test'
d8e2b4a target-mips: Add EVA support to P5600
41640a0 target-mips: Implement segmentation control
1b812b6 target-mips: Add segmentation control registers
e68a781 target-mips: Add an MMU mode for ERL
a4d378b target-mips: Abstract mmu_idx from hflags
4331ffd target-mips: Check memory permissions with mem_idx
0b20e7b target-mips: Decode EVA load & store instructions
f813a87 target-mips: Prepare loads/stores for EVA
75eb9a9 target-mips: Add CP0_Ebase.WG (write gate) support

=== OUTPUT BEGIN ===
Checking PATCH 1/9: target-mips: Add CP0_Ebase.WG (write gate) support...
ERROR: space prohibited after that '&' (ctx:WxW)
#104: FILE: target-mips/op_helper.c:1529:
+    if (arg1 & (1 << CP0EBase_WG) & env->CP0_EBase_rw_bitmask) {
                                   ^

ERROR: space prohibited after that '&' (ctx:WxW)
#116: FILE: target-mips/op_helper.c:1540:
+    if (arg1 & (1 << CP0EBase_WG) & env->CP0_EBase_rw_bitmask) {
                                   ^

total: 2 errors, 0 warnings, 119 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 2/9: target-mips: Prepare loads/stores for EVA...
Checking PATCH 3/9: target-mips: Decode EVA load & store instructions...
Checking PATCH 4/9: target-mips: Check memory permissions with mem_idx...
Checking PATCH 5/9: target-mips: Abstract mmu_idx from hflags...
Checking PATCH 6/9: target-mips: Add an MMU mode for ERL...
ERROR: trailing statements should be on next line
#94: FILE: target-mips/op_helper.c:97:
+    case 3: cpu_##insn##_error_ra(env, addr, val, retaddr); break;      \

total: 1 errors, 0 warnings, 65 lines checked

Your patch has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

Checking PATCH 7/9: target-mips: Add segmentation control registers...
Checking PATCH 8/9: target-mips: Implement segmentation control...
Checking PATCH 9/9: target-mips: Add EVA support to P5600...
=== OUTPUT END ===

Test command exited with code: 1


---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@freelists.org