From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45365) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bhVYf-0004rm-B7 for qemu-devel@nongnu.org; Wed, 07 Sep 2016 01:38:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bhVYa-0004TX-BK for qemu-devel@nongnu.org; Wed, 07 Sep 2016 01:38:00 -0400 Date: Wed, 7 Sep 2016 15:34:59 +1000 From: David Gibson Message-ID: <20160907053459.GM2780@voom.fritz.box> References: <1472797976-24210-1-git-send-email-nikunj@linux.vnet.ibm.com> <1472797976-24210-4-git-send-email-nikunj@linux.vnet.ibm.com> <20160907040252.GJ2780@voom.fritz.box> <87d1kgjoy9.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="9Jdw4pA1x1k2W7MG" Content-Disposition: inline In-Reply-To: <87d1kgjoy9.fsf@abhimanyu.i-did-not-set--mail-host-address--so-tickle-me> Subject: Re: [Qemu-devel] [PATCH RFC 3/4] target-ppc: use atomic_cmpxchg for ld/st reservation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, alex.bennee@linaro.org, rth@twiddle.net, qemu-devel@nongnu.org, benh@kernel.crashing.org --9Jdw4pA1x1k2W7MG Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 07, 2016 at 10:17:42AM +0530, Nikunj A Dadhania wrote: > David Gibson writes: >=20 > > [ Unknown signature status ] > > On Fri, Sep 02, 2016 at 12:02:55PM +0530, Nikunj A Dadhania wrote: > >> Signed-off-by: Nikunj A Dadhania > > > > This really needs a comment indicating that this implementation isn't > > strictly correct (although probably good enough in practice). >=20 > Sure. And it also does not help if someone uses any store other than > store conditional, that isn't taken care. >=20 > Assumption here is the locking primitives use load with reservation and > store conditional. And no other ld/st variant touch this memory. So, a) I don't think this really relies on that: an ordinary store (assuming it changes the value) will still get picked up the cmpxchg. Well.. at least after a suitable memory barrier. Matching memory models between emulated and host cpus is a whole other kettle of fish. I think this does matter, IIRC a kernel spin unlock on ppc is a barrier + plain store, no load locked or store conditional. > > Specifically a racing store which happens to store the same value > > which was already in memory should clobber the reservation, but won't > > with this implementation. > > > > I had a long discussion at KVM Forum with Emilio Costa about this, in > > which I discovered just how hard it is to strictly implement > > store-conditional semantics in terms of anything else. So, this is > > probably a reasonable substitute, but we should note the fact that > > it's not 100%. >=20 > I will update the commit log. >=20 > Regards, > Nikunj >=20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --9Jdw4pA1x1k2W7MG Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJXz6cDAAoJEGw4ysog2bOS6zYQALKLmBvBEkbB2N0dRQkNbH82 KPJVYUjh1/6oqTPLwyasiKYWXDDnnYczz/mzfo7tvZRtGj587uFR1Ta7HfKBKPlO U2x/3L3ou/cbnys5kT3Osbzwb3nI6kZnQcF4+baCL+VbzO9E7Ixdyhv/ZwwlzWVx S8aWNxFMqhvZpqGLqVwUtS/OZrPKD9k319AV6hWZgD2XOquwAJ5nx7lEZ2jS2KwB jA3zfiG/F0AbXloIjSX8rCsUUOpNH2OFaFQFW9l4wpMpzbgXzz5Ng12Tq6kVEPe8 Xpu3axTEOYIvtRJKgwdRB7GqzebmtB5VK1soFkR85itG9J5Cd0WHLu0/aDL+eX6N TEdUo+HvOJ7+FIYo39+CZlAXZuhqOwDj4Fpz4i6YvT/SRT8QYhTmiIV+GQQzcrpP kz7H5KWVFFvxtnojCvfTFHoHuxppGFvIOjo5R70obRYFA66f19KHKFCxlAnkgJ3f /4Exxv3eXXm9hNDycqbjJWRrhGrcATtSVnHmqinJzN7Q0asIU/eAJmqpn/Uw3EM9 Gl+Td7c9NS2mpI6qQZI7Rq6tAlCw96NeyNVAf0F4yNJ62a4Dstu/mYNrhUMsZqfQ ytlkqyxtK+qwJWzLakR/e/ZgQm7QHrTWoK8FxKis++SfAdweHseWXVgjTnV6zbqV VIOzqEWz5XxF40Gzjryc =Etfq -----END PGP SIGNATURE----- --9Jdw4pA1x1k2W7MG--