From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:46571) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkKV5-0000fN-Qv for qemu-devel@nongnu.org; Wed, 14 Sep 2016 20:26:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkKV0-0004UA-3W for qemu-devel@nongnu.org; Wed, 14 Sep 2016 20:25:59 -0400 Date: Thu, 15 Sep 2016 10:25:31 +1000 From: David Gibson Message-ID: <20160915002531.GE15077@voom.fritz.box> References: <1473832442-17762-1-git-send-email-nikunj@linux.vnet.ibm.com> <1473832442-17762-4-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="S0QU+l03nqHlODqK" Content-Disposition: inline In-Reply-To: <1473832442-17762-4-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v4 3/3] target-ppc: tlbie/tlbivax should have global effect List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, benh@kernel.crashing.org, alex.bennee@linaro.org, qemu-devel@nongnu.org, rth@twiddle.net --S0QU+l03nqHlODqK Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 14, 2016 at 11:24:02AM +0530, Nikunj A Dadhania wrote: > tlbie (BookS) and tlbivax (BookE) plus the H_CALLs(pseries) should have > a global effect. >=20 > Introduces TLB_NEED_GLOBAL_FLUSH flag. During lazy tlb flush, after > taking care of pending local flushes, check broadcast flush(at context > synchronizing event ptesync/tlbsync, etc) is needed. Depending on the > bitmask state of the tlb_need_flush, tlb is flushed from other cpus if > needed and the flags are cleared. >=20 > Suggested-by: Benjamin Herrenschmidt > Signed-off-by: Nikunj A Dadhania > --- > hw/ppc/spapr_hcall.c | 2 ++ > target-ppc/cpu.h | 1 + > target-ppc/helper_regs.h | 17 +++++++++++++++++ > target-ppc/mmu-hash64.c | 2 +- > target-ppc/mmu_helper.c | 10 +++++++--- > target-ppc/translate.c | 6 ++++++ > 6 files changed, 34 insertions(+), 4 deletions(-) >=20 > diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c > index ef12ea0..6144e17 100644 > --- a/hw/ppc/spapr_hcall.c > +++ b/hw/ppc/spapr_hcall.c > @@ -319,6 +319,8 @@ static target_ulong h_protect(PowerPCCPU *cpu, sPAPRM= achineState *spapr, > ppc_hash64_store_hpte(cpu, pte_index, > (v & ~HPTE64_V_VALID) | HPTE64_V_HPTE_DIRTY, 0= ); > ppc_hash64_tlb_flush_hpte(cpu, pte_index, v, r); > + /* Flush the tlb */ > + check_tlb_flush(env, 1); > /* Don't need a memory barrier, due to qemu's global lock */ > ppc_hash64_store_hpte(cpu, pte_index, v | HPTE64_V_HPTE_DIRTY, r); > return H_SUCCESS; > diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h > index 71111dc..50fe0f5 100644 > --- a/target-ppc/cpu.h > +++ b/target-ppc/cpu.h > @@ -1010,6 +1010,7 @@ struct CPUPPCState { > bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active = */ > uint32_t tlb_need_flush; /* Delayed flush needed */ > #define TLB_NEED_LOCAL_FLUSH 0x1 > +#define TLB_NEED_GLOBAL_FLUSH 0x2 > #endif > =20 > /* Other registers */ > diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h > index bcf65ce..fd2c961 100644 > --- a/target-ppc/helper_regs.h > +++ b/target-ppc/helper_regs.h > @@ -161,6 +161,23 @@ static inline void check_tlb_flush(CPUPPCState *env,= uint32_t global) > tlb_flush(cs, 1); > env->tlb_need_flush &=3D ~TLB_NEED_LOCAL_FLUSH; > } > + > + /* Propagate TLB invalidations to other CPUs when the guest uses bro= adcast > + * TLB invalidation instructions. > + */ > + if (global && (env->tlb_need_flush & TLB_NEED_GLOBAL_FLUSH)) { > + CPUState *other_cs; > + CPU_FOREACH(other_cs) { > + if (other_cs !=3D cs) { > + PowerPCCPU *cpu =3D POWERPC_CPU(other_cs); > + CPUPPCState *other_env =3D &cpu->env; > + > + other_env->tlb_need_flush &=3D ~TLB_NEED_LOCAL_FLUSH; > + tlb_flush(other_cs, 1); > + } > + } > + env->tlb_need_flush &=3D ~TLB_NEED_GLOBAL_FLUSH; > + } > } > #else > static inline void check_tlb_flush(CPUPPCState *env, uint32_t global) { } > diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c > index 1f52b64..fdb7a78 100644 > --- a/target-ppc/mmu-hash64.c > +++ b/target-ppc/mmu-hash64.c > @@ -912,7 +912,7 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, > * invalidate, and we still don't have a tlb_flush_mask(env, n, > * mask) in QEMU, we just invalidate all TLBs > */ > - tlb_flush(CPU(cpu), 1); > + cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_F= LUSH; > } > =20 > void ppc_hash64_update_rmls(CPUPPCState *env) > diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c > index bf9f329..1dd057a 100644 > --- a/target-ppc/mmu_helper.c > +++ b/target-ppc/mmu_helper.c > @@ -2757,7 +2757,7 @@ static inline void booke206_invalidate_ea_tlb(CPUPP= CState *env, int tlbn, > =20 > void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) > { > - PowerPCCPU *cpu =3D ppc_env_get_cpu(env); > + CPUState *cs; > =20 > if (address & 0x4) { > /* flush all entries */ > @@ -2774,11 +2774,15 @@ void helper_booke206_tlbivax(CPUPPCState *env, ta= rget_ulong address) > if (address & 0x8) { > /* flush TLB1 entries */ > booke206_invalidate_ea_tlb(env, 1, address); > - tlb_flush(CPU(cpu), 1); > + CPU_FOREACH(cs) { > + tlb_flush(cs, 1); > + } > } else { > /* flush TLB0 entries */ > booke206_invalidate_ea_tlb(env, 0, address); > - tlb_flush_page(CPU(cpu), address & MAS2_EPN_MASK); > + CPU_FOREACH(cs) { > + tlb_flush_page(cs, address & MAS2_EPN_MASK); > + } Why are these explicit CPU_FOREACH()s instead of using the flags you've just built? > } > } > =20 > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > index 5026804..d96ff66 100644 > --- a/target-ppc/translate.c > +++ b/target-ppc/translate.c > @@ -4448,6 +4448,7 @@ static void gen_tlbie(DisasContext *ctx) > #if defined(CONFIG_USER_ONLY) > GEN_PRIV; > #else > + TCGv_i32 t1; > CHK_HV; > =20 > if (NARROW_MODE(ctx)) { > @@ -4458,6 +4459,11 @@ static void gen_tlbie(DisasContext *ctx) > } else { > gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); > } > + t1 =3D tcg_temp_new_i32(); > + tcg_gen_ld_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); > + tcg_gen_ori_i32(t1, t1, TLB_NEED_GLOBAL_FLUSH); > + tcg_gen_st_i32(t1, cpu_env, offsetof(CPUPPCState, tlb_need_flush)); > + tcg_temp_free_i32(t1); > #endif /* defined(CONFIG_USER_ONLY) */ > } > =20 --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --S0QU+l03nqHlODqK Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIcBAEBAgAGBQJX2ep7AAoJEGw4ysog2bOS1+4P/1QMwE5VMZTut7Sh3ShrCi9/ qLLnwpfacgTbrwDpkNY8Evo9KOGV09WFQGq0vpWbJdDB5s3MhgC5f4ohF1f+FBQK c7DkfKirsZ2DrMPIemw9z4BY52zqKbQW3nE/2jyPmV1MW/WwMrMNOq/aFXtNbw5T kYDeSFtjD5VL4S+0kvhXvliOcZI7O3qqLPjTmEJC8oh11LncOQa8Z4L+qTpP/Fcp j9IL63KXHlbA3NsW/rxv8UlLiJ8UaywQ1R9ekwENBiLaPID0pX+JuEXinNzy7fXp qMQ05L3UV+NM9pK524FJVmaJV1J7GWCBedKSYvYsrDeKN5a0CEfDhJ/Uc1JJqtdF Dx+CtTjBp67G2qiqNKfksAzoQQn+zo07lHnxb93bIjgk+GpZAsRG8T0wglGPsug1 USRvz4Q8k7JlEXxc6oxn/bkpVYetrpv7aOeerAG8bmdDcu/USfFJtzNZyAWlwIko Bjanl+JWMlsIu7rL+mQdVpvVEfQLF6TXfRSrYhipQ7M+NnNb9mkhFdl2EL84dZuV yrRftiM5nCfrBVH/XPBl1OLysUrR1uwIBcmBvYmlewQYn1gXi00P7tsKLGD7Mj2E JXtyKHnmxAcALlmZHcXeTesXH9brx8Kzl3EHvjlhV4qZ97hka3Wvp3sXXCEf0VyE pY4zwzPeu08lOOd/Bvav =sP7s -----END PGP SIGNATURE----- --S0QU+l03nqHlODqK--