From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:45281) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bkNYG-0005dC-VH for qemu-devel@nongnu.org; Wed, 14 Sep 2016 23:41:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bkNYC-0004Om-4k for qemu-devel@nongnu.org; Wed, 14 Sep 2016 23:41:28 -0400 Date: Thu, 15 Sep 2016 11:46:00 +1000 From: David Gibson Message-ID: <20160915014600.GM15077@voom.fritz.box> References: <1473662506-27441-1-git-send-email-nikunj@linux.vnet.ibm.com> <1473662506-27441-18-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha1; protocol="application/pgp-signature"; boundary="8aUgEFSDYDA6u3T0" Content-Disposition: inline In-Reply-To: <1473662506-27441-18-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH RESEND v2 17/17] target-ppc: add stxvb16x and stxvh8x List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org, benh@kernel.crashing.org --8aUgEFSDYDA6u3T0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 12, 2016 at 12:11:46PM +0530, Nikunj A Dadhania wrote: > stxvb16x: Store VSX Vector Byte*16 > stxvh8x: Store VSX Vector Halfword*8 >=20 > Signed-off-by: Nikunj A Dadhania Basically the same comments as on the load side - this looks bogus to me. I think it would make sense to fold together the corresponding load and store patches - makes it easier to review that they're doing matching things. > --- > target-ppc/translate/vsx-impl.inc.c | 55 +++++++++++++++++++++++++++++++= ++++++ > target-ppc/translate/vsx-ops.inc.c | 2 ++ > 2 files changed, 57 insertions(+) >=20 > diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/v= sx-impl.inc.c > index f2fc5f9..20afe3b 100644 > --- a/target-ppc/translate/vsx-impl.inc.c > +++ b/target-ppc/translate/vsx-impl.inc.c > @@ -165,6 +165,61 @@ static void gen_lxvh8x(DisasContext *ctx) > tcg_temp_free(EA); > } > =20 > +static void gen_stxvb16x(DisasContext *ctx) > +{ > + TCGv_i64 xsh =3D cpu_vsrh(xS(ctx->opcode)); > + TCGv_i64 xsl =3D cpu_vsrl(xS(ctx->opcode)); > + TCGv EA; > + > + if (unlikely(!ctx->vsx_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VSXU); > + return; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + EA =3D tcg_temp_new(); > + gen_addr_reg_index(ctx, EA); > + > + if (ctx->le_mode) { > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); > + } else { > + gen_helper_bswap32x2(xsh, xsh); > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + gen_helper_bswap32x2(xsl, xsl); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); > + } > + tcg_temp_free(EA); > +} > + > +static void gen_stxvh8x(DisasContext *ctx) > +{ > + TCGv_i64 xsh =3D cpu_vsrh(xS(ctx->opcode)); > + TCGv_i64 xsl =3D cpu_vsrl(xS(ctx->opcode)); > + TCGv EA; > + > + if (unlikely(!ctx->vsx_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VSXU); > + return; > + } > + gen_set_access_type(ctx, ACCESS_INT); > + EA =3D tcg_temp_new(); > + gen_addr_reg_index(ctx, EA); > + if (ctx->le_mode) { > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_BEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_BEQ); > + } else { > + gen_helper_bswap32x2(xsh, xsh); > + tcg_gen_qemu_st_i64(xsh, EA, ctx->mem_idx, MO_LEQ); > + tcg_gen_addi_tl(EA, EA, 8); > + gen_helper_bswap32x2(xsl, xsl); > + tcg_gen_qemu_st_i64(xsl, EA, ctx->mem_idx, MO_LEQ); > + } > + tcg_temp_free(EA); > +} > + > #define VSX_STORE_SCALAR(name, operation) \ > static void gen_##name(DisasContext *ctx) \ > { \ > diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vs= x-ops.inc.c > index 598b349..f5afa0f 100644 > --- a/target-ppc/translate/vsx-ops.inc.c > +++ b/target-ppc/translate/vsx-ops.inc.c > @@ -17,6 +17,8 @@ GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PP= C2_VSX207), > GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207), > GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX), > GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX), > +GEN_HANDLER_E(stxvh8x, 0x1F, 0x0C, 0x1D, 0, PPC_NONE, PPC2_ISA300), > +GEN_HANDLER_E(stxvb16x, 0x1F, 0x0C, 0x1F, 0, PPC_NONE, PPC2_ISA300), > =20 > GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX2= 07), > GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX2= 07), --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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