From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42368) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bmrfZ-00058y-U0 for qemu-devel@nongnu.org; Wed, 21 Sep 2016 20:15:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bmrfW-0001ME-Um for qemu-devel@nongnu.org; Wed, 21 Sep 2016 20:15:17 -0400 Date: Thu, 22 Sep 2016 10:14:29 +1000 From: David Gibson Message-ID: <20160922001429.GK1809@umbus.fritz.box> References: <1474266577-11704-1-git-send-email-nikunj@linux.vnet.ibm.com> <1474266577-11704-10-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="lZZ4ablUVnt2XgAh" Content-Disposition: inline In-Reply-To: <1474266577-11704-10-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v4 9/9] ppc/xics: move set_nr_{irqs, servers} to xics.c List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, benh@kernel.crashing.org, clg@kaod.org --lZZ4ablUVnt2XgAh Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Mon, Sep 19, 2016 at 11:59:37AM +0530, Nikunj A Dadhania wrote: > Get this duplicate code in the base implementation. >=20 > Signed-off-by: Nikunj A Dadhania > --- > hw/intc/xics.c | 74 ++++++++++++++++++++++++++++++++++++++++++++-= ------ > hw/intc/xics_kvm.c | 34 +++-------------------- > hw/intc/xics_native.c | 51 +++++++++++++++++++++-------------- > hw/intc/xics_spapr.c | 49 +++++++++------------------------- > include/hw/ppc/xics.h | 19 ++++++++++--- > 5 files changed, 126 insertions(+), 101 deletions(-) >=20 > diff --git a/hw/intc/xics.c b/hw/intc/xics.c > index 4ac2d00..9fbf962 100644 > --- a/hw/intc/xics.c > +++ b/hw/intc/xics.c > @@ -54,8 +54,9 @@ int xics_get_cpu_index_by_dt_id(int cpu_dt_id) > void xics_cpu_destroy(XICSState *xics, PowerPCCPU *cpu) > { > CPUState *cs =3D CPU(cpu); > - ICPState *ss =3D &xics->ss[cs->cpu_index]; > + ICPState *ss; > =20 > + ss =3D xics->ss + sizeof(ICPState) * cs->cpu_index; > assert(cs->cpu_index < xics->nr_servers); > assert(cs =3D=3D ss->cs); > =20 > @@ -67,9 +68,10 @@ void xics_cpu_setup(XICSState *xics, PowerPCCPU *cpu) > { > CPUState *cs =3D CPU(cpu); > CPUPPCState *env =3D &cpu->env; > - ICPState *ss =3D &xics->ss[cs->cpu_index]; > + ICPState *ss; > XICSStateClass *info =3D XICS_COMMON_GET_CLASS(xics); > =20 > + ss =3D xics->ss + sizeof(ICPState) * cs->cpu_index; > assert(cs->cpu_index < xics->nr_servers); > =20 > ss->cs =3D cs; > @@ -101,10 +103,12 @@ static void xics_common_reset(DeviceState *d) > { > XICSState *xics =3D XICS_COMMON(d); > ICSState *ics; > + ICPState *ss; > int i; > =20 > for (i =3D 0; i < xics->nr_servers; i++) { > - device_reset(DEVICE(&xics->ss[i])); > + ss =3D xics->ss + sizeof(ICPState) * i; > + device_reset(DEVICE(ss)); > } > =20 > QLIST_FOREACH(ics, &xics->ics, list) { > @@ -193,6 +197,7 @@ static void xics_common_initfn(Object *obj) > XICSState *xics =3D XICS_COMMON(obj); > =20 > QLIST_INIT(&xics->ics); > + xics->ss_class =3D object_class_by_name(TYPE_ICP); > object_property_add(obj, "nr_irqs", "int", > xics_prop_get_nr_irqs, xics_prop_set_nr_irqs, > NULL, NULL, NULL); > @@ -201,7 +206,15 @@ static void xics_common_initfn(Object *obj) > NULL, NULL, NULL); > =20 > /* For exclusive use of monitor command */ > - g_xics =3D XICS_COMMON(obj); > + g_xics =3D xics; Looks like this change should be folded into the patch introducing g_xics. > +} > + > +static void xics_common_realize(DeviceState *dev, Error **errp) > +{ > + XICSState *xics =3D XICS_COMMON(dev); > + XICSStateClass *xsc =3D XICS_COMMON_GET_CLASS(xics); > + > + xsc->realize(dev, errp); > } > =20 > static void xics_common_class_init(ObjectClass *oc, void *data) > @@ -209,6 +222,7 @@ static void xics_common_class_init(ObjectClass *oc, v= oid *data) > DeviceClass *dc =3D DEVICE_CLASS(oc); > =20 > dc->reset =3D xics_common_reset; > + dc->realize =3D xics_common_realize; > } > =20 > static const TypeInfo xics_common_info =3D { > @@ -277,7 +291,7 @@ static void icp_check_ipi(ICPState *ss) > =20 > static void icp_resend(XICSState *xics, int server) > { > - ICPState *ss =3D xics->ss + server; > + ICPState *ss =3D xics->ss + server * sizeof(ICPState); > ICSState *ics; > =20 > if (ss->mfrr < CPPR(ss)) { > @@ -290,7 +304,7 @@ static void icp_resend(XICSState *xics, int server) > =20 > void icp_set_cppr(XICSState *xics, int server, uint8_t cppr) > { > - ICPState *ss =3D xics->ss + server; > + ICPState *ss =3D xics->ss + server * sizeof(ICPState); > uint8_t old_cppr; > uint32_t old_xisr; > =20 > @@ -317,7 +331,7 @@ void icp_set_cppr(XICSState *xics, int server, uint8_= t cppr) > =20 > void icp_set_mfrr(XICSState *xics, int server, uint8_t mfrr) > { > - ICPState *ss =3D xics->ss + server; > + ICPState *ss =3D xics->ss + server * sizeof(ICPState); > =20 > ss->mfrr =3D mfrr; > if (mfrr < CPPR(ss)) { > @@ -349,7 +363,7 @@ uint32_t icp_ipoll(ICPState *ss, uint32_t *mfrr) > =20 > void icp_eoi(XICSState *xics, int server, uint32_t xirr) > { > - ICPState *ss =3D xics->ss + server; > + ICPState *ss =3D xics->ss + server * sizeof(ICPState); > ICSState *ics; > uint32_t irq; > =20 > @@ -370,7 +384,7 @@ void icp_eoi(XICSState *xics, int server, uint32_t xi= rr) > static void icp_irq(ICSState *ics, int server, int nr, uint8_t priority) > { > XICSState *xics =3D ics->xics; > - ICPState *ss =3D xics->ss + server; > + ICPState *ss =3D xics->ss + server * sizeof(ICPState); > =20 > trace_xics_icp_irq(server, nr, priority); > =20 > @@ -488,6 +502,14 @@ static const TypeInfo icp_info =3D { > .class_size =3D sizeof(ICPStateClass), > }; > =20 > +static const TypeInfo icp_native_info =3D { > + .name =3D TYPE_NATIVE_ICP, > + .parent =3D TYPE_ICP, > + .instance_size =3D sizeof(ICPNative), > + .class_init =3D icp_class_init, > + .class_size =3D sizeof(ICPStateClass), > +}; > + Introducing a whole new subclass doesn't seem to be covered by the commit message... > /* > * ICS: Source layer > */ > @@ -689,7 +711,7 @@ void xics_hmp_info_pic(Monitor *mon, const QDict *qdi= ct) > uint32_t i; > =20 > for (i =3D 0; i < g_xics->nr_servers; i++) { > - ICPState *icp =3D &g_xics->ss[i]; > + ICPState *icp =3D g_xics->ss + i * sizeof(ICPState); > =20 > if (!icp->output) { > continue; > @@ -829,12 +851,44 @@ void ics_set_irq_type(ICSState *ics, int srcno, boo= l lsi) > lsi ? XICS_FLAGS_IRQ_LSI : XICS_FLAGS_IRQ_MSI; > } > =20 > +void xics_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp) > +{ > + ICSState *ics =3D QLIST_FIRST(&xics->ics); > + > + /* This needs to be deprecated ... */ Could you actually deprecate this, instead of moving it around? > + xics->nr_irqs =3D nr_irqs; > + if (ics) { > + ics->nr_irqs =3D nr_irqs; > + } > +} > + > +void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **e= rrp) > +{ > + int i; > + const char *typename =3D object_class_get_name(xics->ss_class); > + size_t size =3D object_type_get_instance_size(typename); > + > + xics->nr_servers =3D nr_servers; > + > + xics->ss =3D g_malloc0(xics->nr_servers * size); > + for (i =3D 0; i < xics->nr_servers; i++) { > + char buffer[32]; > + void *obj; > + > + obj =3D xics->ss + size * i; > + object_initialize(obj, size, typename); > + snprintf(buffer, sizeof(buffer), "icp[%d]", i); > + object_property_add_child(OBJECT(xics), buffer, obj, errp); > + } > +} > + > static void xics_register_types(void) > { > type_register_static(&xics_common_info); > type_register_static(&ics_simple_info); > type_register_static(&ics_base_info); > type_register_static(&icp_info); > + type_register_static(&icp_native_info); > } > =20 > type_init(xics_register_types) > diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c > index 89862df..b095b9e 100644 > --- a/hw/intc/xics_kvm.c > +++ b/hw/intc/xics_kvm.c > @@ -362,35 +362,6 @@ static void xics_kvm_cpu_setup(XICSState *xics, Powe= rPCCPU *cpu) > } > } > =20 > -static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, > - Error **errp) > -{ > - ICSState *ics =3D QLIST_FIRST(&xics->ics); > - > - /* This needs to be deprecated ... */ > - xics->nr_irqs =3D nr_irqs; > - if (ics) { > - ics->nr_irqs =3D nr_irqs; > - } > -} > - > -static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers, > - Error **errp) > -{ > - int i; > - > - xics->nr_servers =3D nr_servers; > - > - xics->ss =3D g_malloc0(xics->nr_servers * sizeof(ICPState)); > - for (i =3D 0; i < xics->nr_servers; i++) { > - char buffer[32]; > - object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_KVM_IC= P); > - snprintf(buffer, sizeof(buffer), "icp[%d]", i); > - object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss= [i]), > - errp); > - } > -} > - > static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr, > uint32_t token, > uint32_t nargs, target_ulong args, > @@ -492,6 +463,7 @@ static void xics_kvm_initfn(Object *obj) > XICSState *xics =3D XICS_COMMON(obj); > ICSState *ics; > =20 > + xics->ss_class =3D object_class_by_name(TYPE_KVM_ICP); > ics =3D ICS_SIMPLE(object_new(TYPE_ICS_KVM)); > object_property_add_child(obj, "ics", OBJECT(ics), NULL); > ics->xics =3D xics; > @@ -505,8 +477,8 @@ static void xics_kvm_class_init(ObjectClass *oc, void= *data) > =20 > dc->realize =3D xics_kvm_realize; > xsc->cpu_setup =3D xics_kvm_cpu_setup; > - xsc->set_nr_irqs =3D xics_kvm_set_nr_irqs; > - xsc->set_nr_servers =3D xics_kvm_set_nr_servers; > + xsc->set_nr_irqs =3D xics_set_nr_irqs; > + xsc->set_nr_servers =3D xics_set_nr_servers; > } > =20 > static const TypeInfo xics_spapr_kvm_info =3D { > diff --git a/hw/intc/xics_native.c b/hw/intc/xics_native.c > index 26e45cc..db2fd4d 100644 > --- a/hw/intc/xics_native.c > +++ b/hw/intc/xics_native.c > @@ -38,11 +38,19 @@ > /* #define DEBUG_MM(fmt...) printf(fmt) */ > #define DEBUG_MM(fmt...) do { } while (0) > =20 > +typedef struct XICSNative { > + /*< private >*/ > + XICSState xics; > + > + /*< public >*/ > + MemoryRegion icp_mmio; > +} XICSNative; > + > static void xics_native_initfn(Object *obj) > { > - XICSState *xics =3D XICS_NATIVE(obj); > + XICSState *xics =3D XICS_COMMON(obj); > =20 > - QLIST_INIT(&xics->ics); > + xics->ss_class =3D object_class_by_name(TYPE_NATIVE_ICP); ss_class should be a class field, not an instance field. > } > =20 > static uint64_t icp_mm_read(void *opaque, hwaddr addr, unsigned width) > @@ -51,6 +59,7 @@ static uint64_t icp_mm_read(void *opaque, hwaddr addr, = unsigned width) > int32_t cpu_id, server; > uint32_t val; > ICPState *ss; > + ICPNative *icpn; > bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); > =20 > cpu_id =3D (addr & (ICP_MM_SIZE - 1)) >> 12; > @@ -59,7 +68,8 @@ static uint64_t icp_mm_read(void *opaque, hwaddr addr, = unsigned width) > fprintf(stderr, "XICS: Bad ICP server %d\n", server); > goto bad_access; > } > - ss =3D &s->ss[server]; > + icpn =3D s->ss + server * sizeof(ICPNative); > + ss =3D &icpn->icp; > =20 > switch (addr & 0xffc) { > case 0: /* poll */ > @@ -88,21 +98,21 @@ static uint64_t icp_mm_read(void *opaque, hwaddr addr= , unsigned width) > break; > case 16: > if (width =3D=3D 4) { > - val =3D ss->links[0]; > + val =3D icpn->links[0]; > } else { > goto bad_access; > } > break; > case 20: > if (width =3D=3D 4) { > - val =3D ss->links[1]; > + val =3D icpn->links[1]; > } else { > goto bad_access; > } > break; > case 24: > if (width =3D=3D 4) { > - val =3D ss->links[2]; > + val =3D icpn->links[2]; > } else { > goto bad_access; > } > @@ -125,7 +135,7 @@ static void icp_mm_write(void *opaque, hwaddr addr, u= int64_t val, > { > XICSState *s =3D opaque; > int32_t cpu_id, server; > - ICPState *ss; > + ICPNative *icpn; > bool byte0 =3D (width =3D=3D 1 && (addr & 0x3) =3D=3D 0); > =20 > cpu_id =3D (addr & (ICP_MM_SIZE - 1)) >> 12; > @@ -134,7 +144,8 @@ static void icp_mm_write(void *opaque, hwaddr addr, u= int64_t val, > fprintf(stderr, "XICS: Bad ICP server %d\n", server); > goto bad_access; > } > - ss =3D &s->ss[server]; > + icpn =3D s->ss + server * sizeof(ICPNative); > + ss =3D &icpn->icp; > =20 > DEBUG_MM("icp_mm_write(addr=3D%016llx,serv=3D0x%x/%d,off=3D%d,w=3D%d= ,val=3D0x%08x)\n", > (unsigned long long)addr, cpu_id, server, > @@ -159,21 +170,21 @@ static void icp_mm_write(void *opaque, hwaddr addr,= uint64_t val, > break; > case 16: > if (width =3D=3D 4) { > - ss->links[0] =3D val; > + icpn->links[0] =3D val; > } else { > goto bad_access; > } > break; > case 20: > if (width =3D=3D 4) { > - ss->links[1] =3D val; > + icpn->links[1] =3D val; > } else { > goto bad_access; > } > break; > case 24: > if (width =3D=3D 4) { > - ss->links[2] =3D val; > + icpn->links[2] =3D val; > } else { > goto bad_access; > } > @@ -245,8 +256,9 @@ void xics_create_native_icp_node(XICSState *s, void *= fdt, > =20 > static void xics_native_realize(DeviceState *dev, Error **errp) > { > - XICSState *s =3D XICS_NATIVE(dev); > - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); > + XICSNative *n =3D XICS_NATIVE(dev); > + XICSState *s =3D XICS_COMMON(dev); > + SysBusDevice *sbd =3D SYS_BUS_DEVICE(s); > Error *error =3D NULL; > int i; > =20 > @@ -256,13 +268,14 @@ static void xics_native_realize(DeviceState *dev, E= rror **errp) > } > =20 > /* Register MMIO regions */ > - memory_region_init_io(&s->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp", > + memory_region_init_io(&n->icp_mmio, OBJECT(s), &icp_mm_ops, s, "icp", > ICP_MM_SIZE); > - sysbus_init_mmio(sbd, &s->icp_mmio); > + sysbus_init_mmio(sbd, &n->icp_mmio); > sysbus_mmio_map(sbd, 0, ICP_MM_BASE); > =20 > for (i =3D 0; i < s->nr_servers; i++) { > - object_property_set_bool(OBJECT(&s->ss[i]), true, "realized", &e= rror); > + ICPNative *icpn =3D s->ss + i * sizeof(ICPNative); > + object_property_set_bool(OBJECT(icpn), true, "realized", &error); > if (error) { > error_propagate(errp, error); > return; > @@ -272,20 +285,18 @@ static void xics_native_realize(DeviceState *dev, E= rror **errp) > =20 > static void xics_native_class_init(ObjectClass *oc, void *data) > { > - DeviceClass *dc =3D DEVICE_CLASS(oc); > XICSStateClass *xsc =3D XICS_NATIVE_CLASS(oc); > =20 > - dc->realize =3D xics_native_realize; > + xsc->realize =3D xics_native_realize; > xsc->set_nr_servers =3D xics_set_nr_servers; > } > =20 > static const TypeInfo xics_native_info =3D { > .name =3D TYPE_XICS_NATIVE, > .parent =3D TYPE_XICS_COMMON, > - .instance_size =3D sizeof(XICSState), > + .instance_size =3D sizeof(XICSNative), > .class_size =3D sizeof(XICSStateClass), > .class_init =3D xics_native_class_init, > - .instance_init =3D xics_native_initfn, > }; > =20 > static void xics_native_register_types(void) > diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c > index 4dd1399..0644942 100644 > --- a/hw/intc/xics_spapr.c > +++ b/hw/intc/xics_spapr.c > @@ -67,7 +67,8 @@ static target_ulong h_xirr(PowerPCCPU *cpu, sPAPRMachin= eState *spapr, > target_ulong opcode, target_ulong *args) > { > CPUState *cs =3D CPU(cpu); > - uint32_t xirr =3D icp_accept(spapr->xics->ss + cs->cpu_index); > + uint32_t xirr =3D icp_accept(spapr->xics->ss + > + cs->cpu_index * sizeof(ICPState)); > =20 > args[0] =3D xirr; > return H_SUCCESS; > @@ -77,9 +78,11 @@ static target_ulong h_xirr_x(PowerPCCPU *cpu, sPAPRMac= hineState *spapr, > target_ulong opcode, target_ulong *args) > { > CPUState *cs =3D CPU(cpu); > - ICPState *ss =3D &spapr->xics->ss[cs->cpu_index]; > - uint32_t xirr =3D icp_accept(ss); > + ICPState *ss; > + uint32_t xirr; > =20 > + ss =3D spapr->xics->ss + cs->cpu_index * sizeof(ICPState); > + xirr =3D icp_accept(ss); > args[0] =3D xirr; > args[1] =3D cpu_get_host_ticks(); > return H_SUCCESS; > @@ -100,7 +103,8 @@ static target_ulong h_ipoll(PowerPCCPU *cpu, sPAPRMac= hineState *spapr, > { > CPUState *cs =3D CPU(cpu); > uint32_t mfrr; > - uint32_t xirr =3D icp_ipoll(spapr->xics->ss + cs->cpu_index, &mfrr); > + uint32_t xirr =3D icp_ipoll(spapr->xics->ss + > + cs->cpu_index * sizeof(ICPState), &mfrr); > =20 > args[0] =3D xirr; > args[1] =3D mfrr; > @@ -234,35 +238,6 @@ static void rtas_int_on(PowerPCCPU *cpu, sPAPRMachin= eState *spapr, > rtas_st(rets, 0, RTAS_OUT_SUCCESS); > } > =20 > -static void xics_spapr_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, > - Error **errp) > -{ > - ICSState *ics =3D QLIST_FIRST(&xics->ics); > - > - /* This needs to be deprecated ... */ > - xics->nr_irqs =3D nr_irqs; > - if (ics) { > - ics->nr_irqs =3D nr_irqs; > - } > -} > - > -static void xics_spapr_set_nr_servers(XICSState *xics, uint32_t nr_serve= rs, > - Error **errp) > -{ > - int i; > - > - xics->nr_servers =3D nr_servers; > - > - xics->ss =3D g_malloc0(xics->nr_servers * sizeof(ICPState)); > - for (i =3D 0; i < xics->nr_servers; i++) { > - char buffer[32]; > - object_initialize(&xics->ss[i], sizeof(xics->ss[i]), TYPE_ICP); > - snprintf(buffer, sizeof(buffer), "icp[%d]", i); > - object_property_add_child(OBJECT(xics), buffer, OBJECT(&xics->ss= [i]), > - errp); > - } > -} > - > static void xics_spapr_realize(DeviceState *dev, Error **errp) > { > XICSState *xics =3D XICS_SPAPR(dev); > @@ -297,8 +272,8 @@ static void xics_spapr_realize(DeviceState *dev, Erro= r **errp) > } > =20 > for (i =3D 0; i < xics->nr_servers; i++) { > - object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized", > - &error); > + ICPState *ss =3D xics->ss + i * sizeof(ICPState); > + object_property_set_bool(OBJECT(ss), true, "realized", &error); > if (error) { > error_propagate(errp, error); > return; > @@ -319,8 +294,8 @@ static void xics_spapr_class_init(ObjectClass *oc, vo= id *data) > XICSStateClass *xsc =3D XICS_SPAPR_CLASS(oc); > =20 > dc->realize =3D xics_spapr_realize; > - xsc->set_nr_irqs =3D xics_spapr_set_nr_irqs; > - xsc->set_nr_servers =3D xics_spapr_set_nr_servers; > + xsc->set_nr_irqs =3D xics_set_nr_irqs; > + xsc->set_nr_servers =3D xics_set_nr_servers; > } > =20 > static const TypeInfo xics_spapr_info =3D { > diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h > index 58bb7c6..0a427d7 100644 > --- a/include/hw/ppc/xics.h > +++ b/include/hw/ppc/xics.h > @@ -45,7 +45,7 @@ > OBJECT_CHECK(KVMXICSState, (obj), TYPE_XICS_SPAPR_KVM) > =20 > #define TYPE_XICS_NATIVE "xics-native" > -#define XICS_NATIVE(obj) OBJECT_CHECK(XICSState, (obj), TYPE_XICS_NATIVE) > +#define XICS_NATIVE(obj) OBJECT_CHECK(XICSNative, (obj), TYPE_XICS_NATIV= E) > =20 > #define XICS_COMMON_CLASS(klass) \ > OBJECT_CLASS_CHECK(XICSStateClass, (klass), TYPE_XICS_COMMON) > @@ -71,6 +71,7 @@ typedef struct XICSStateClass XICSStateClass; > typedef struct XICSState XICSState; > typedef struct ICPStateClass ICPStateClass; > typedef struct ICPState ICPState; > +typedef struct ICPNative ICPNative; > typedef struct ICSStateClass ICSStateClass; > typedef struct ICSState ICSState; > typedef struct ICSIRQState ICSIRQState; > @@ -78,6 +79,7 @@ typedef struct ICSIRQState ICSIRQState; > struct XICSStateClass { > DeviceClass parent_class; > =20 > + DeviceRealize realize; > void (*cpu_setup)(XICSState *icp, PowerPCCPU *cpu); > void (*set_nr_irqs)(XICSState *icp, uint32_t nr_irqs, Error **errp); > void (*set_nr_servers)(XICSState *icp, uint32_t nr_servers, Error **= errp); > @@ -89,9 +91,9 @@ struct XICSState { > /*< public >*/ > uint32_t nr_servers; > uint32_t nr_irqs; > - ICPState *ss; > + void *ss; > + ObjectClass *ss_class; > QLIST_HEAD(, ICSState) ics; > - MemoryRegion icp_mmio; > }; > =20 > #define TYPE_ICP "icp" > @@ -100,6 +102,9 @@ struct XICSState { > #define TYPE_KVM_ICP "icp-kvm" > #define KVM_ICP(obj) OBJECT_CHECK(ICPState, (obj), TYPE_KVM_ICP) > =20 > +#define TYPE_NATIVE_ICP "icp-native" > +#define NATIVE_ICP(obj) OBJECT_CHECK(ICPNative, (obj), TYPE_NATIVE_ICP) > + > #define ICP_CLASS(klass) \ > OBJECT_CLASS_CHECK(ICPStateClass, (klass), TYPE_ICP) > #define ICP_GET_CLASS(obj) \ > @@ -123,6 +128,12 @@ struct ICPState { > uint8_t mfrr; > qemu_irq output; > bool cap_irq_xics_enabled; > +}; > + > +struct ICPNative { > + /**/ > + ICPState icp; > + /**/ > uint32_t links[3]; > }; > =20 > @@ -199,6 +210,8 @@ void xics_spapr_free(XICSState *icp, int irq, int num= ); > =20 > void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); > void xics_cpu_destroy(XICSState *icp, PowerPCCPU *cpu); > +void xics_set_nr_irqs(XICSState *xics, uint32_t nr_irqs, Error **errp); > +void xics_set_nr_servers(XICSState *xics, uint32_t nr_servers, Error **e= rrp); > =20 > void xics_create_native_icp_node(XICSState *s, void *fdt, > uint32_t base, uint32_t count); --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. 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