From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bpR34-0000mV-FD for qemu-devel@nongnu.org; Wed, 28 Sep 2016 22:26:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bpR33-0002Ap-7V for qemu-devel@nongnu.org; Wed, 28 Sep 2016 22:26:10 -0400 Date: Thu, 29 Sep 2016 11:29:23 +1000 From: David Gibson Message-ID: <20160929012923.GA8390@umbus.fritz.box> References: <1475040687-27523-1-git-send-email-nikunj@linux.vnet.ibm.com> <1475040687-27523-3-git-send-email-nikunj@linux.vnet.ibm.com> MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="bp/iNruPH9dso1Pn" Content-Disposition: inline In-Reply-To: <1475040687-27523-3-git-send-email-nikunj@linux.vnet.ibm.com> Subject: Re: [Qemu-devel] [PATCH v4 2/9] target-ppc: Implement mtvsrdd instruction List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Nikunj A Dadhania Cc: qemu-ppc@nongnu.org, rth@twiddle.net, qemu-devel@nongnu.org, benh@kernel.crashing.org, Ravi Bangoria --bp/iNruPH9dso1Pn Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Wed, Sep 28, 2016 at 11:01:20AM +0530, Nikunj A Dadhania wrote: > From: Ravi Bangoria >=20 > mtvsrdd: Move To VSR Double Doubleword >=20 > Signed-off-by: Ravi Bangoria > Signed-off-by: Nikunj A Dadhania > --- > target-ppc/translate/vsx-impl.inc.c | 23 +++++++++++++++++++++++ > target-ppc/translate/vsx-ops.inc.c | 1 + > 2 files changed, 24 insertions(+) >=20 > diff --git a/target-ppc/translate/vsx-impl.inc.c b/target-ppc/translate/v= sx-impl.inc.c > index b669e8c..f9db1d4 100644 > --- a/target-ppc/translate/vsx-impl.inc.c > +++ b/target-ppc/translate/vsx-impl.inc.c > @@ -234,6 +234,29 @@ static void gen_mfvsrld(DisasContext *ctx) > tcg_gen_mov_i64(cpu_gpr[rA(ctx->opcode)], cpu_vsrl(xS(ctx->opcode))); > } > =20 > +static void gen_mtvsrdd(DisasContext *ctx) > +{ > + if (xT(ctx->opcode) < 32) { > + if (unlikely(!ctx->vsx_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VSXU); > + return; > + } > + } else { > + if (unlikely(!ctx->altivec_enabled)) { > + gen_exception(ctx, POWERPC_EXCP_VPU); > + return; > + } > + } Huh.. so in the ISA doc version I have at least (p114), the pseudo-code for the instruction states either vector or VSX exceptions. The text however says either FP or vector exceptions. The pseudo-code version seems more sensible which is what you've implemented, so I'm guessing this is just an error in the descriptive text. It'd be nice to confirm that against real hardware behaviour if possible though. > + > + if (!rA(ctx->opcode)) { > + tcg_gen_movi_i64(cpu_vsrh(xT(ctx->opcode)), 0); > + } else { > + tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode= )]); > + } > + > + tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_gpr[rB(ctx->opcode)]); > +} > + > #endif > =20 > static void gen_xxpermdi(DisasContext *ctx) > diff --git a/target-ppc/translate/vsx-ops.inc.c b/target-ppc/translate/vs= x-ops.inc.c > index 3b296f8..1287973 100644 > --- a/target-ppc/translate/vsx-ops.inc.c > +++ b/target-ppc/translate/vsx-ops.inc.c > @@ -23,6 +23,7 @@ GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PP= C_NONE, PPC2_VSX207), > GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX20= 7), > GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX20= 7), > GEN_HANDLER_E(mfvsrld, 0X1F, 0x13, 0x09, 0x0000F800, PPC_NONE, PPC2_ISA3= 00), > +GEN_HANDLER_E(mtvsrdd, 0X1F, 0x13, 0x0D, 0x0, PPC_NONE, PPC2_ISA300), > #endif > =20 > #define GEN_XX1FORM(name, opc2, opc3, fl2) \ --=20 David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_ | _way_ _around_! http://www.ozlabs.org/~dgibson --bp/iNruPH9dso1Pn Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- Version: GnuPG v2 iQIcBAEBCAAGBQJX7G5zAAoJEGw4ysog2bOSNT4P/Rk9mhIOBVWw+RoY8/8+sDnj r8W35dsHCzxyFJcrhXyZ3DjF0PTNbJb0sK6+WXYo5XlW52IWZJACJ29sWdiy6hbf ZaJGVuISpdbnsIcfSrZbfspGaX2VDn6HO1v+G3buXNjyDozuE0KGD47YuCMvk6qc jeF2vEsNFHb0VISBxDo1FxPBYVlW7C/ldS5NOjJLODv5iHwres8Wd/qeIFF59Xvs oRAyowgpj8lkLQBwWwPK7NDpUyOLj23BTF/iSb08cSPMR5YjncCKCRZLzeh9w2RV LlBZbhCIc2wOmLt9O3tozel9r0WLKRdKxEvboguWeDCZmqO2IkKyIeoPLNiLljDC mqSBptg+vloNT4VLHVEzKFTSeDyUySEiC1lmah+kTk12HeAblkDp6eSIx5H/eNEk 18LJT+DePCeWsAxhq0sSH5VVpwpJ4+yGqEs5rzsTgjf4PzidVFJDFbFGNtjz2NZ8 USHLGTA2iqO/QOw+AUnO7RX7t/oL85i0HGhYCVVmH9XeHYgaLjwwL/eh6s4+JzH7 fjsLLUnlKEdQlRkj2mTimmRMyMHUeAOQegWiLO2TNWTJUmSa8g1/OPtZmTyhsbp6 b7N/hUMrT8hPvMu5p43GfGTm//GZELkeStJPYgp24mxZQ1EdBbxNvDNv+o6VTW12 icLKjJlwTjwElsDOa61G =83Va -----END PGP SIGNATURE----- --bp/iNruPH9dso1Pn--