From: David Gibson <david@gibson.dropbear.id.au>
To: Richard Henderson <rth@twiddle.net>
Cc: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>,
qemu-ppc@nongnu.org, qemu-devel@nongnu.org,
benh@kernel.crashing.org,
Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Subject: Re: [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction
Date: Thu, 29 Sep 2016 11:53:25 +1000 [thread overview]
Message-ID: <20160929015325.GD8390@umbus.fritz.box> (raw)
In-Reply-To: <ab290e38-f7d0-b368-1752-cbba6fe6f416@twiddle.net>
[-- Attachment #1: Type: text/plain, Size: 835 bytes --]
On Wed, Sep 28, 2016 at 01:21:00PM -0700, Richard Henderson wrote:
> On 09/28/2016 11:41 AM, Nikunj A Dadhania wrote:
> > + tcg_gen_mov_i64(t0, cpu_gpr[rA(ctx->opcode)]);
> > + tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), t0, t0, 32, 32);
>
> Why are you using t0?
Richard, I don't quite understand your question. This looks correct
to me. It's duplicating the low 32-bits of rA into both the low-and
high 32-bits of t0, which will then be store to both the low and high
64-bit elements of the VSR. That matches the instruction definition
which puts the low 32-bits of RA into every 32-bit element of the
vector.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
next prev parent reply other threads:[~2016-09-29 2:26 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-28 18:41 [Qemu-devel] [PATCH v5 0/9] POWER9 TCG enablements - part4 Nikunj A Dadhania
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 1/9] target-ppc: Implement mfvsrld instruction Nikunj A Dadhania
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 2/9] target-ppc: Implement mtvsrdd instruction Nikunj A Dadhania
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 3/9] target-ppc: Implement mtvsrws instruction Nikunj A Dadhania
2016-09-28 20:21 ` Richard Henderson
2016-09-29 1:53 ` David Gibson [this message]
2016-09-29 4:07 ` Richard Henderson
2016-09-29 2:19 ` Nikunj A Dadhania
2016-09-29 4:08 ` Richard Henderson
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 4/9] target-ppc: improve lxvw4x implementation Nikunj A Dadhania
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 5/9] target-ppc: improve stxvw4x implementation Nikunj A Dadhania
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 6/9] target-ppc: add lxvh8x instruction Nikunj A Dadhania
2016-09-28 20:22 ` Richard Henderson
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 7/9] target-ppc: add stxvh8x instruction Nikunj A Dadhania
2016-09-28 20:23 ` Richard Henderson
2016-09-28 18:41 ` [Qemu-devel] [PATCH v5 8/9] target-ppc: add lxvb16x instruction Nikunj A Dadhania
2016-09-28 18:42 ` [Qemu-devel] [PATCH v5 9/9] target-ppc: add stxvb16x instruction Nikunj A Dadhania
2016-09-29 1:51 ` [Qemu-devel] [PATCH v5 0/9] POWER9 TCG enablements - part4 David Gibson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20160929015325.GD8390@umbus.fritz.box \
--to=david@gibson.dropbear.id.au \
--cc=benh@kernel.crashing.org \
--cc=nikunj@linux.vnet.ibm.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-ppc@nongnu.org \
--cc=ravi.bangoria@linux.vnet.ibm.com \
--cc=rth@twiddle.net \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).